AVSS + 0.4V < (CAPN or CAPP) < AVDD
0.4V
-
Gain Control
PGA[2:0] Bits
MUX (+)
MUX ( )
-
CHOP
Chopping Control CHOP Bit
AVSS
CAPP
300
W
300
W
A
1
A
2
AVDD
CAPN
(55k , typ
Modulator
Effective
Impedance
W
)
10nF
10
Frequency (Hz)
100
10
1
PGANoise(nV/
)
Ö
Hz
100
1k
PGA CHOP Off
PGA CHOP On
f =
P
1
6.3
600
C
´
´
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
9.6 PGA (Programmable Gain Amplifier)
PGA (Programmable Gain
Amplifier) (continued)
The PGA of the ADS1282 is a low-noise, continuous-
time, differential-in/differential-out CMOS amplifier.
The gain is programmable from 1 to 64, set by
register bits, PGA[2:0]. The PGA differentially drives
the modulator through 300
Ω
internal resistors. A C0G
capacitor (10nF typical) must be connected to CAPP
and CAPN to filter modulator sampling glitches. The
external capacitor also serves as an anti-alias filter.
The corner frequency is given in
(3)
Referring to
, amplifiers A
1
and A
2
are
chopped to remove the offset, offset drift, and the 1/f
noise. Chopping moves the effects to f
CLK
/128 (8kHz),
which is safely out of the passband. Chopping can be
disabled by setting the CHOP register bit = 0. When
Figure 30. PGA Noise
chopping is disabled, the input impedance of the PGA
increases
substantially
(100G
Ω
).
As
shown
in
, chopping maintains flat noise density; if
The PGA has programmable gains from 1 to 64.
chopping is disabled, however, it results in a rising 1/f
shows the register bit setting for the PGA and
noise profile.
resulting full-scale differential range.
Table 3. PGA Gain Settings
DIFFERENTIAL
INPUT RANGE
PGA[2:0]
GAIN
000
1
±2.5
001
2
±1.25
010
4
±0.625
011
8
±0.312
100
16
±0.156
101
32
±0.078
110
64
±0.039
(1) V
REF
= 5V.
The specified output operating range of the PGA is
shown in
(4)
Figure 29. PGA Block Diagram
PGA output levels (signal plus common-mode) should
be maintained within these limits for best operation.
14
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