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Y[n] = 3M0[n
2]
6M0[n
3] + 4M0[n
4]
+ 9(M1[n]
2M1[n
1] + M1[n
2])
-
-
-
-
-
-
-
2nd-Order
2nd-Stage
DS
2nd-Order
1st-Stage
DS
Analog Input (V )
IN
4th-Order Modulator
MCLK
M0
M1
f
CLK
/4
Magnitude(dB)
Frequency (Hz)
0
-
20
-
40
-
60
-
80
-
100
-
180
1
10
100
100k
1k
10k
-
120
-
140
-
160
1Hz Resolution
V
= 20mV
IN
DC
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
9.7 ADC
Modulator (continued)
The ADC block of the ADS1282 is composed of two
appears at the chopping frequency (f
CLK
/512 = 8kHz).
sections:
a
high-accuracy
modulator
and
a
The component at 5.8kHz is the tone frequency,
programmable digital filter.
shifted out of band by an external 20mV/PGA offset.
The frequency of the tone is proportional to the
9.8 Modulator
applied dc input and is given by PGA × V
IN
/0.003 (in
kHz).
The high-performance modulator is an inherently-
stable, fourth-order,
ΔΣ
, 2 + 2 pipelined structure, as
shows. It shifts the quantization noise to a
higher frequency (out of the passband) where digital
filtering can easily remove it. The modulator can be
filtered either by the on-chip digital filter or by use of
post-processing filters.
Figure 32. Modulator Output Spectrum
9.9 Modulator Over-Range
Figure 31. Fourth-Order Modulator
The ADS1282 modulator is inherently stable, and
therefore, has predictable recovery behavior resulting
The modulator first stage converts the analog input
from an input overdrive condition. The modulator
voltage into a pulse-code modulated (PCM) stream.
does not exhibit self-resetting behavior, which often
When the level of differential analog input (AINP –
results in an unstable output data stream.
AINN) is near one-half the level of the reference
voltage 1/2 × (VREFP – VREFN), the ‘1’ density of
The ADS1282 modulator outputs a 1s density data
the PCM data stream is at its highest. When the level
stream at 90% duty cycle with the positive full-scale
of the differential analog input is near zero, the PCM
input signal applied (10% duty cycle with the negative
‘0’ and ‘1’ densities are nearly equal. At the two
full-scale signal). If the input is overdriven past 90%
extremes of the analog input levels (+FS and –FS),
modulation, but below 100% modulation (10% and
the ‘1’ density of the PCM streams is approximately
0%
for
negative
overdrive,
respectively),
the
+90% and +10%, respectively.
modulator remains stable and continues to output the
1s density data stream. The digital filter may or may
The modulator second stage produces a '1' density
not clip the output codes to +FS or –FS, depending
data stream designed to cancel the quantization
on the duration of the overdrive. When the input
noise of the first stage. The data streams of the two
returns to the normal range from a long duration
stages are then combined before the digital filter
overdrive
(worst
case),
the
modulator
returns
stage, as shown in
immediately to the normal range, but the group delay
of the digital filter delays the return of the conversion
(5)
result to within the linear range (31 readings for linear
phase FIR). 31 additional readings (62 total) are
M0[n] represents the most recent first-stage output
required for completely settled data.
while M0[n – 1] is the previous first-stage output.
When the modulator output is enabled, the digital
If the inputs are sufficiently overdriven to drive the
filter shuts down to save power.
modulator to full duty cycle, all 1s or all 0s, the
modulator enters a stable saturated state. The digital
The modulator is optimized for input signals within a
output code may clip to +FS or –FS, again depending
4kHz passband. As
shows, the noise
on the duration. A small duration overdrive may not
shaping of the modulator results in a sharp increase
always clip the output code. When the input returns to
in noise above 6kHz. The modulator has a chopped
input structure that further reduces noise within the
passband. The noise moves out of the passband and
Copyright © 2007–2015, Texas Instruments Incorporated
15
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