TPMC917 User Manual Issue 1.0.7
Page 5 of 26
Table of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6
FIGURE 2-1 : TECHNICAL SPECIFICATION...................................................................................................8
FIGURE 3-1 : PCI9030 LOCAL SPACE CONFIGURATION ............................................................................9
FIGURE 3-2 : SRAM MEMORY MAP .............................................................................................................10
FIGURE 3-3 : LOCAL REGISTER MEMORY MAP ........................................................................................10
FIGURE 3-4 : REGISTER SET 1 ....................................................................................................................11
FIGURE 3-5 : REGISTER SET 2 ....................................................................................................................11
FIGURE 3-6 : SPECIAL REGISTER ...............................................................................................................12
FIGURE 3-7 : FIFO READY REGISTER CHANNEL 0-3 ................................................................................12
FIGURE 3-8 : INTERRUPT STATUS REGISTER (ADDRESS 0X21) ............................................................13
FIGURE 4-1 : PCI9030 HEADER....................................................................................................................14
FIGURE 4-2 : PCI9030 PCI BASE ADDRESS USAGE ..................................................................................15
FIGURE 4-3 : PCI9030 LOCAL CONFIGURATION REGISTER FOR TPMC917-10.....................................16
FIGURE 4-4 : CONFIGURATION EEPROM TPMC917-10 ............................................................................17
FIGURE 5-1 : INTERRUPT CONTROL/STATUS REGISTER (INTCSR, 0X4C)............................................19
FIGURE 5-2 : LOCAL BUS LITTLE/BIG ENDIAN...........................................................................................20
FIGURE 6-1 : DIP SWITCH POSITION ..........................................................................................................23
FIGURE 6-2 : DIP SWITCH SETTINGS FOR BATTERY BACKUP BY ON BOARD LITHIUM CELL ...........23
FIGURE 6-3 : DIP SWITCH SETTINGS FOR BATTERY BACKUP VIA P14 I/O CONNECTOR...................24
FIGURE 6-4 : DIP SWITCH SETTINGS FOR BATTERY BACKUP DISABLED ............................................24
FIGURE 7-1 : MEZZANINE P14 I/O CONNECTOR .......................................................................................25
FIGURE 7-2 : P14 PIN ASSIGNMENT ...........................................................................................................25
FIGURE 7-3 : FRONT PANEL DB25 FEMALE CONNECTOR (TPMC917-10 ONLY)...................................26
FIGURE 7-4 : DB25 PIN ASSIGNMENT.........................................................................................................26
