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Tews Technologies TPMC917-10, User Manual

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Tews Technologies TPMC917-10 User Manual Download Page 17

 

 

TPMC917 User Manual Issue 1.0.7 

Page 17 of 26 

4.3 

 

 Configuration EEPROM 

After power-on or PCI reset, the PCI9030 loads initial configuration register data from the on board 
configuration EEPROM. 

The configuration EEPROM contains the following configuration data: 

•

  Address 0x00 to 0x27 : PCI9030 PCI Configuration Register Values 

•

  Address 0x28 to 0x87 : PCI9030 Local Configuration Register Values 

See the PCI9030 Manual for more information. 

Address 

Offset 

 

0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 

0x00  0x0395 0x1498 0x0281 0x0000 0x0880 0x000A  s.b. 0x1498 

0x10  0x0000 0x0040 0x0000 0x0100 0x4801 0x4801 0x0000 0x0000 

0x20  0x0000 0x0006 0x0000 0x0003  s.b. 0x0000 

0x0FFF 

0xFFC0 

0x30  0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 

0x40  0x0040 0x0001 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 

0x50  0x4082 0x0100 0x5401 0xA0E0 0x0000 0x0000 0x0000 0x0000 

0x60  0x0000 0x0000 0x0010 0x0001 0x0030 0x0001 0x0040 0x0011 

0x70  0x0040 0x0023 0x0000  s.b. 0x807C 

0x5000 

0x0249 

0x06D3 

0x80  0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0x90  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xA0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xB0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xC0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xD0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xE0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xF0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

Figure 4-4 :  Configuration EEPROM TPMC917-10 

TPMC917-10: 

0x0C = 0x000A, 

0x76 = 0x005B   

0x28 = 0x0FC0 

TPMC917-20: 

0x0C = 0x0014,  

0x76 = 0x005A   

0x28 = 0x0FC0 

TPMC917-21: 

0x0C = 0x0015,  

0x76 = 0x005A   

0x28 = 0x0FE0 

Summary of Contents for TPMC917-10

Page 1: ...0 7 November 2008 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 25469 Halstenbek Germany www tews com Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e mail info tews com 9190 Double Diamond...

Page 2: ...urate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage ari...

Page 3: ...hium Battery August 2004 1 3 TPMC917 20 added March 2005 1 4 PCI Class Code changed PCI Header and EEPROM Correction June 2005 1 5 New address TEWS LLC September 2006 1 6 TPMC917 21 added Correction i...

Page 4: ...3 3 2 2 Interrupt Status Register 13 4 PCI9030 TARGET CHIP 14 4 1 PCI Configuration Registers PCR 14 4 1 1 PCI9030 Header TPMC917 10 14 4 1 2 PCI Base Address Initialization 15 4 2 Local Configuration...

Page 5: ...PCI9030 PCI BASE ADDRESS USAGE 15 FIGURE 4 3 PCI9030 LOCAL CONFIGURATION REGISTER FOR TPMC917 10 16 FIGURE 4 4 CONFIGURATION EEPROM TPMC917 10 17 FIGURE 5 1 INTERRUPT CONTROL STATUS REGISTER INTCSR 0...

Page 6: ...ime any further accesses to the SRAM are not possible A miniature DIP switch allows the selection of the battery backup source either from the on board lithium cell or from an external battery via the...

Page 7: ...mum Transfer Rate Up to 115 2 kbps 2 5nF and 3kohm load impedance ESD Protection 15kV Human Body Model 6kV IEC1000 4 2 model SRAM Interface Memory Capacity TPMC917 10 20 4 Mbyte 2 banks organized as 5...

Page 8: ...load on serial ports TPMC917 10 only 12V 360 A typical no load on serial ports TPMC917 10 only Power Requirements Battery backup 1 6 A typical 25 C Temperature Range Operating Storage 0 C to 70 C 55 C...

Page 9: ...PCI9030 local spaces PCI9030 Local Space PCI9030 PCI Base Address Offset in PCI Configuration Space PCI Space Mapping Size Byte Port Width Bit Endian Mode Description 0 0x18 MEM 4 MByte 2 MByte 32 Ba...

Page 10: ...M TPMC917 10 20 TPMC917 21 Figure 3 2 SRAM Memory Map All local registers of the TPMC917 are accessible in the memory space of the PMC module Address range PCI Base Address 3 for Local Address Space 1...

Page 11: ...egister 8 0x04 Modem Control Register Modem Control Register 8 0x05 Line Status Register LCR 8 0x06 Modem Status Register 8 0x07 Scratchpad Register Scratchpad Register 8 Figure 3 4 Register Set 1 To...

Page 12: ...smit and receive FIFOs of channel 0 to channel 3 Each TX and RX channel 0 3 has its own 64 byte FIFO If any of the TX RX FIFOs become empty full the status bit associated with the TX RX function of ch...

Page 13: ...nal battery is lower than the specified battery fault voltage R W 0 5 INT Status Bat2 0 4 INT Status Bat1 Interrupt Status Battery 1 2 1 indicates interrupt is pending on corresponding battery monitor...

Page 14: ...ocal Address Space 1 Y s b 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 PCI CardBus Information Structure Pointer N 00...

Page 15: ...mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the...

Page 16: ...al Re map Register Space 3 0x0000_0000 Not used 0x24 Local Re map Register ROM 0x0000_0000 Not used 0x28 Local Address Space 0 Descriptor 0x0082_0100 Local timing address space 0 0x2C Local Address Sp...

Page 17: ...x0001 0x40 0x0040 0x0001 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x50 0x4082 0x0100 0x5401 0xA0E0 0x0000 0x0000 0x0000 0x0000 0x60 0x0000 0x0000 0x0010 0x0001 0x0030 0x0001 0x0040 0x0011 0x70 0x0040...

Page 18: ...I Adapter Software Reset bit is set in the PCI9030 local configuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset Value of 1 resets the PCI9030 and issues a reset to the Local Bus...

Page 19: ...UART Interrupt Status R 0 1 Local Interrupt 1 Polarity R W 1 0 Local Interrupt 1 Enable R W 1 TPMC917 10 0 TPMC917 20 21 Figure 5 1 Interrupt Control Status Register INTCSR 0x4C The local interrupt 1...

Page 20: ...6 Byte 1 D 15 8 Byte 2 D 15 8 Byte 2 D 23 16 Byte 3 D 7 0 Byte 3 D 31 24 16 Bit upper lane 16 Bit Byte 0 D 31 24 Byte 0 D 7 0 Byte 1 D 23 16 Byte 1 D 15 8 16 Bit lower lane Byte 0 D 15 8 Byte 1 D 7 0...

Page 21: ...fset Name LAS0BRD 0x28 Local Address Space 0 Bus Region Description Register LAS1BRD 0x2C Local Address Space 0 Bus Region Description Register LAS2BRD 0x30 Local Address Space 0 Bus Region Descriptio...

Page 22: ...equipment with the correct polarity and Do not use metallic or other conductive extraction tools to replace the batteries Do not attempt to revive used batteries by heating charging or other means Do...

Page 23: ...A four position miniature DIP switch is used to select the source for battery backup Factory configuration is switched S3 S4 in position ON and S1 S2 in position OFF to provide battery backup by the...

Page 24: ...and the battery has to be changed To use the interrupt based battery monitor function of the TPMC917 the interrupts must be enabled in the Interrupt Control Status Register INTCSR of the PCI target c...

Page 25: ...External battery supply 2 NC Not connected 3 Bat_Ext External battery supply 4 NC Not connected 5 Bat_Ext External battery supply 6 NC Not connected 7 GND Board Ground 8 NC Not connected 9 GND Board...

Page 26: ...UART C 9 GND Board Ground 10 TXD Transmit Data UART D 11 RTSD Request to Send UART D 12 GND Board Ground 13 NC Not connected 14 RXA Receive Data UART A 15 CTSA Clear to Send UART A 16 NC Not connecte...

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