TPMC917 User Manual Issue 1.0.7
Page 13 of 26
3.3.2.2 Interrupt Status Register
The Interrupt Status Register is a byte wide read / write register located in the PCI Memory Space
(PCI Base Address 3 + 0x21) and is useful for fast interrupt source detection.
It reflects the interrupt status of the four UART channels and the two Battery Status Interrupts.
The battery interrupts can be enabled and disabled.
Bit
Symbol
Description
Access
Reset
Value
7
0
6
Enable
Battery INT
Enable the Battery Monitor Interrupt
00 = Interrupt from battery monitor is disabled.
Any other value enables the Battery Monitor Interrupt.
After reset both battery interrupts are disabled.
Both battery monitor devices generate interrupts on the local
interrupt 2 of the PCI target chip if the monitored battery voltage
(on board Lithium Cell or external battery) is lower than the
specified battery fault voltage.
R/W
0
5
INT Status
Bat2
0
4
INT Status
Bat1
Interrupt Status Battery 1/2
1 = indicates interrupt is pending on corresponding battery
monitor
(TPMC917-21: only “INT Status BAT 1” carries valid data)
R
0
3
Interrupt
Channel 3
2
Interrupt
Channel 2
1
Interrupt
Channel 1
0
Interrupt
Channel 0
Interrupt Status of Channel 0-3
1 = indicates interrupt is pending on channel 0-3
0 = no interrupt on channel 0-3
Each of the four serial channels generates interrupts on the
local interrupt 1 of the PCI target chip.
If the “PCI Interrupt Enable” of the PCI target chip is disabled
(Interrupt Control/Status Register bit 6 is set to ‘0’). This register
can be used as a polling register for interrupts of the four serial
controllers.
Interrupts from the four serial channels can be individual
enabled by the ST16C654 serial controller. After reset all UART
interrupts are disabled.
For TPMC917-20/21, these bits carry random data.
R 0
Figure 3-8 : Interrupt Status Register (Address 0x21)
