TPMC917 User Manual Issue 1.0.7
Page 12 of 26
3.3.2 Special Registers
The TMPC917 provides two special registers. For fast status detection there is a FIFO Status Register
for channel 0 to channel 3, and an Interrupt Status Register for all four channels and the battery
interrupts.
For TPMC917-20/21, only the battery interrupt bits of the Interrupt Status Register carry valid data.
Offset to PCI Base Address 3
Register Name
Size (bit)
0x20
FIFO Ready Register CH0-CH3
8
0x21
Interrupt Status Register
8
Figure 3-6 : Special Register
3.3.2.1 FIFO Ready Register Channel 0-3 (TPMC917-10 only)
The FIFO Ready Register FIFORDY1 is a byte wide read only register. The FIFO Ready Register
provides the status of the transmit and receive FIFOs of channel 0 to channel 3. Each TX and RX
channel (0-3) has its own 64 byte FIFO. If any of the TX/RX FIFOs become empty/full, the status bit
associated with the TX/RX function of channel 0-3 is set in the FIFO Ready Register.
For TPMC917-20/21, this register carries random data.
Bit
Symbol
Description
Access
Reset
Value
7
RXRDY
Channel 3
6
RXRDY
Channel 2
5
RXRDY
Channel 1
4
RXRDY
Channel 0
RX Ready Bit for channel 0-3
1 = the receiver is ready and is below the programmed trigger
level
0 = the corresponding receive FIFO is above the programmed
trigger level or a time-out has occurred
R
3
TXRDY
Channel 3
2
TXRDY
Channel 2
1
TXRDY
Channel 1
0
TXRDY
Channel 0
TX Ready Bit for channel 0-3
1 = one or more empty locations exist in the corresponding
FIFO
0 = the corresponding transmit FIFO is full. This channel will not
accept any more transmit data.
R
Figure 3-7 : FIFO Ready Register Channel 0-3
