Tews Technologies TPMC917-10, User Manual

Page: 11 / 26

TPMC917 User Manual Issue 1.0.7 Page 11 of 26
3.3.1 Register Set of each UART channel (TPMC917-10 only)
Each of the four serial channels of the TPMC917-10 is accessed in the PCI memory space by two sets
of registers. Both register sets have a common register, the Line Control Register (LCR). Bit 7 of the
LCR is used to switch between the two register sets of a channel.
Register Set 1 is only accessible if bit 7 of the LCR (PCI Base Address 3 + Channel 0x03) is
set to ‘0’. After reset Register Set 1 is accessible.
PCI Base A
Channel Read Mode Write Mode Size (bit)
0x00 Receive Holding Register Transmit Holding Register 8
0x01 Interrupt Enable Register Interrupt Enable Register 8
0x02 Interrupt Status Register FIFO Control Register 8
0x03 Line Control Register Line Control Register 8
0x04 Modem Control Register Modem Control Register 8
0x05 Line Status Register (LCR) - 8
0x06 Modem Status Register - 8
0x07 Scratchpad Register Scratchpad Register 8
Figure 3-4 : Register Set 1
To get access to Register Set 2 of the serial channels bit 7 of the LCR must be set to ‘1’. The
Enhanced Feature Registers, Xon-1/2 and Xoff-1/2 registers are only accessible if the LCR is set to
‘0xBF’.
PCI Base A
Channel READ/WRITE Size (bit) Comment
0x00 LSB of Divisor Latch 8 LCR bit 7 set to ‘1’
0x01 MSB of Divisor Latch 8 LCR bit 7 set to ‘1’
0x02 Enhanced Feature Register 8 LCR is set to ‘0xBF’
0x03 Line Control Register (LCR) 8 Always accessible
0x04 Xon-1 Word 8 LCR is set to ‘0xBF’
0x05 Xon-2 Word 8 LCR is set to ‘0xBF’
0x06 Xoff-1 Word 8 LCR is set to ‘0xBF’
0x07 Xoff-2 Word 8 LCR is set to ‘0xBF’
Figure 3-5 : Register Set 2
The TPMC917-20/21 has no UARTs. Write access to these registers of a TPMC917-20/21 has no
effect. Reading these registers of a TPMC917-20/21 returns random data.