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Tews Technologies TPMC310, User Manual

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Tews Technologies TPMC310 User Manual Download Page 11

 

 

TPMC310 User Manual Issue 1.1.5 

Page 11 of 22 

3.2.3  CAN Controller Register Space 

PCI Base Address :  

PCI9030 PCI Base Address 3 (Offset 0x1C in PCI9030 PCI Configuration Register Space). 

 

Offset to PCI 

Base Address 

Register Name 

Size 
(Bit) 

CAN Controller Channel 1 

0x000 

CAN Controller CH1 Address 0 

8 

0x001 

CAN Controller CH1 Address 1 

8 

0x002 

CAN Controller CH1 Address 2 

8 

… … 

… 

0x07F 

CAN Controller CH1 Address 127 (dec.) 

8 

0x080 … 0x0FF 

Reserved 

- 

CAN Controller Channel 2 

0x100 

CAN Controller CH2 Address 0 

8 

0x101 

CAN Controller CH2 Address 1 

8 

0x102 

CAN Controller CH2 Address 2 

8 

… … 

… 

0x17F 

CAN Controller CH2 Address 127 (dec.) 

8 

0x180 … 0x1FF 

Reserved 

- 

Table 3-5 :  CAN Controller Register Space 

The CAN controllers must be set to operating mode (CAN Control Register in PLD Register 
Space) before CAN controller register access. 

Please see the SJA1000 CAN Controller Manual for a detailed register description. 

Summary of Contents for TPMC310

Page 1: ...0 Conduction Cooled PMC Isolated 2 x CAN Bus Version 1 1 User Manual Issue 1 1 5 January 2011 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e mail info tews com www tews com ...

Page 2: ...he product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix 0x i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e...

Page 3: ...B Added secondary thermal interface Added extra mounting holes preventing vibration MTBF value has changed Solder pad locations for termination options have changed April 2008 1 1 4 New Notation for User Manual and Engineering Documentation December 2008 1 1 5 1 Corrected I O Line Configuration Table 2 Added note for the Bus_End Option 3 Added note for supported baud rate range to Technical Specif...

Page 4: ...AN Status Register 10 3 2 3 CAN Controller Register Space 11 4 PCI9030 TARGET CHIP 12 4 1 PCI Configuration Registers PCR 12 4 1 1 PCI9030 PCI Header 12 4 1 2 PCI Base Address Initialization 13 4 2 Local Configuration Register LCR 14 4 3 Configuration EEPROM 15 4 4 Local Software Reset 16 5 PROGRAMMING HINTS 17 5 1 CAN Controller SJA1000 17 6 CONFIGURATION HINTS 19 6 1 I O Line Configuration 19 6 ...

Page 5: ...GISTER SPACE 8 TABLE 3 3 CAN CONTROL REGISTER 9 TABLE 3 4 CAN STATUS REGISTER 10 TABLE 3 5 CAN CONTROLLER REGISTER SPACE 11 TABLE 4 1 PCI9030 PCI HEADER 12 TABLE 4 2 PCI9030 LOCAL CONFIGURATION REGISTER 14 TABLE 4 3 CONFIGURATION EEPROM 15 TABLE 5 1 OUTPUT CONTROL REGISTER 17 TABLE 5 2 CLOCK DIVIDER REGISTER 18 TABLE 6 1 I O LINE CONFIGURATION 19 TABLE 6 2 FACTORY DEFAULT I O LINE CONFIGURATION 19...

Page 6: ... two independent channels isolated from system logic and from each other CAN High Speed transceivers are used for the CAN bus I O interface An on board termination option solder pads is provided for each CAN bus channel allowing to configure on board termination and or pass trough mode for the CAN bus The TPMC310 uses the P14 I O connector for the CAN bus I O interface P11 P12 PCI9030 PCI Target C...

Page 7: ...echnology CAN Controller 2 x SJA1000 Philips 16 MHz CAN Bus Transceiver 2 x TJA1050 Philips I O Interface Number of CAN Bus Channels 2 isolated from system logic and from each other CAN Bus Interface CAN High Speed The TJA1050 High Speed CAN Transceiver supports baud rates from 60 kbaud up to 1 Mbaud I O Connector PMC P14 I O 64pin Mezzanine Connector Physical Data Power Requirements 50mA typ 3 3V...

Page 8: ...ping Size Byte Port Width Bit Endian Mode Description 0 2 0x18 MEM 16 8 BIG PLD Register Space 1 3 0x1C MEM 512 8 BIG CAN Controller Register Space 2 4 0x20 Not Used 3 5 0x24 Not Used Table 3 1 PCI9030 Local Space Configuration 3 2 PLD Register Space PCI Base Address PCI9030 PCI Base Address 2 Offset 0x18 in PCI9030 PCI Configuration Register Space Offset to PCI Base Address Register Name Size Bit...

Page 9: ...the CAN controllers are set to reset mode To set the CAN controllers to operating mode the CANx_RST bit must be set to 1 After power up or board reset the CAN bus transceivers are set to silent mode To set the CAN bus transceivers to operating mode the CANx_SEL bit must be set to 1 Disabling interrupts in the CAN Control Register only affects the interrupt mapping to the PCI9030 LINTx local interr...

Page 10: ...ive interrupt request and 1 for active interrupt request Please see the SJA1000 CAN Controller Manual for more information If enabled the CAN CH1 interrupt source is mapped to the PCI9030 LINT1 local interrupt input If enabled the CAN CH2 interrupt source is mapped to the PCI9030 LINT2 local interrupt input The PCI9030 LINTx local interrupt inputs are used in active low level sensitive mode The CA...

Page 11: ...Controller CH1 Address 2 8 0x07F CAN Controller CH1 Address 127 dec 8 0x080 0x0FF Reserved CAN Controller Channel 2 0x100 CAN Controller CH2 Address 0 8 0x101 CAN Controller CH2 Address 1 8 0x102 CAN Controller CH2 Address 2 8 0x17F CAN Controller CH2 Address 127 dec 8 0x180 0x1FF Reserved Table 3 5 CAN Controller Register Space The CAN controllers must be set to operating mode CAN Control Registe...

Page 12: ...l Address Space 0 Y FFFFFFF0 0x1C PCI Base Address 3 for Local Address Space 1 Y FFFFFE00 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 PCI CardBus Information Structure Pointer N 00000000 0x2C Subsystem ID Subsystem Vendor ID N s b 1498 0x30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved New Cap Pt...

Page 13: ...4 the first bit set to 1 determines the size of the required PCI Memory Space size For PCI Expansion ROM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the PCI9030 is requesting a 32 byte space address bits 4 0 are not part of base address decoding 5 ...

Page 14: ...0000 0x14 Local Re map Register Space 0 0x0000_0001 0x18 Local Re map Register Space 1 0x0000_1001 0x1C Local Re map Register Space 2 0x0000_0000 0x20 Local Re map Register Space 3 0x0000_0000 0x24 Local Re map Register ROM 0x0000_0000 0x28 Local Address Space 0 Descriptor 0x1500_C0A0 0x2C Local Address Space 1 Descriptor 0x1502_4120 0x30 Local Address Space 2 Descriptor 0x0000_0000 0x34 Local Add...

Page 15: ...F 0xFE00 0x30 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 0x40 0x0000 0x1001 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x50 0x1500 0xC0A0 0x1502 0x4120 0x0000 0x0000 0x0000 0x0000 0x60 0x0000 0x0000 0x0000 0x0009 0x0000 0x1081 0x0000 0x1181 0x70 0x0000 0x0000 0x0030 0x0049 0x0078 0x0000 0x0224 0x9252 0x80 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x90 0xFFFF 0xFFFF 0xFFFF...

Page 16: ... Adapter Software Reset bit is set in the PCI9030 local configuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset Value of 1 resets the PCI9030 and issues a reset to the Local Bus LRESETo asserted The PCI9030 remains in this reset condition until the PCI Host clears this bit The contents of the PCI9030 PCI and Local Configuration Registers are not reset The PCI9030 PCI Interface...

Page 17: ...us transceivers are held in silent mode To bring the CAN bus transceivers to operating mode the CANx_SEL bit s in the CAN Control Register PLD Register Space must be set Output Control Register The SJA1000 Output Control Register must be programmed as follows for both SJA1000 CAN controllers in the SJA1000 controller internal reset mode see SJA1000 Control Register in the SJA1000 CAN Controller Ma...

Page 18: ...e SJA1000 CAN Controller Manual Bit Symbol Description 7 CAN MODE 0 BasiCAN Mode 1 PeliCAN Mode 6 CBP 1 Bypass input comparator use RX0 only 5 RXINTEN 0 Disable Interrupts on TX1 output 4 0 3 CLOCK OFF 1 Disable Clock Output not used 2 CD2 0 1 CD1 0 0 CD0 0 Table 5 2 Clock Divider Register Baud Rate Range The TPMC310 uses the TJA1050 High Speed CAN transceiver The TJA1050 High Speed CAN Transceive...

Page 19: ...For the bus_end option the I O lines are NOT passed through from the node input pins to the node output pins of the P14 I O connector The node input pins must be used to connect the CAN bus lines see P14 I O pin assignment For the pass_through option the I O lines are passed through from the node input pins to the node output pins of the P14 I O connector see P14 I O pin assignment Termination Mod...

Page 20: ...TPMC310 User Manual Issue 1 1 5 Page 20 of 22 6 2 Solder Pad Location TPMC310 PCB Top View Upper Right Corner Figure 6 1 Solder Pad Location ...

Page 21: ...served 3 Reserved 4 NC 5 Reserved 6 Reserved 7 Reserved 8 NC 9 Reserved 10 Reserved 11 Reserved 12 NC 13 Reserved 14 Reserved 15 Reserved 16 NC 17 NC 18 NC 19 NC 20 NC 21 CAN_CH1_P 22 CAN_CH1_N 23 CAN1_GND 24 NC CAN HS CAN Node CAN Node In 25 CAN_CH1_P 26 CAN_CH1_N 27 CAN1_GND 28 NC CAN HS N A CAN Node Out 29 NC 30 NC 31 NC 32 NC 33 CAN_CH2_P 34 CAN_CH2_N 35 CAN2_GND 36 NC CAN HS CAN Node CAN Node...

Page 22: ...41 64 NC Table 7 1 P14 I O Pin Assignment Be sure that the P14 connector I O signals used by the TPMC310 including the reserved pins are available and not otherwise used on the J14 connector of the PMC carrier board The Out Node for each CAN channel is only available if the on board I O line configuration is set accordingly pass_through mode ...

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