TPMC310 User Manual Issue 1.1.5
Page 10 of 22
3.2.2 CAN Status Register
Bit
Name
Function
Access Reset
7:2
-
Reserved (Undefined for reads)
-
X
1
CAN2_INT
CAN CH2 Controller Interrupt Request Status
R
X
0
CAN1_INT
CAN CH1 Controller Interrupt Request Status
R
X
Table 3-4 : CAN Status Register
The CAN CHx controller interrupt request status is '0' for "no active interrupt request" and '1'
for "active interrupt request".
Please see the SJA1000 CAN Controller Manual for more information.
If enabled, the CAN CH1 interrupt source is mapped to the PCI9030 LINT1# local interrupt input.
If enabled, the CAN CH2 interrupt source is mapped to the PCI9030 LINT2# local interrupt input.
The PCI9030 LINTx# local interrupt inputs are used in active low level sensitive mode.
The CAN interrupts must be acknowledged via SJA1000 registers (CAN Controller Register
Space).
Please see the SJA1000 CAN Controller Manual for more information.
