CAN-Engine
Chapter 4: Software
4-3
4.2
Functions in AE.OBJ
4.2.1
CAN-Engine Initialization
ae_init
This function should be called at the beginning of every program running on CAN-Engine core controllers.
It provides default initialization and configuration of the various I/O pins, interrupt vectors, sets up
expanded DOS I/O, and provides other processor-specific updates needed at the beginning of every
program.
There are certain default pin modes and interrupt settings you might wish to change. With that in mind, the
basic effects of ae_init are described below. For details regarding register use, you will want to refer to the
AMD Am186ES Microcontroller User’s manual.
Initialize the upper chip select to support the default ROM. The CPU registers are configured such
that:
Address space for the ROM is from 0x80000-0xfffff (to map MemCard I/O window)
512K ROM Block size operation.
Three wait state operation (allowing it to support up to 120 ns ROMs). With 70 ns ROMs, this can
actually be set to zero wait state if you require increased performance (at a risk of stability in
noisy environments). For details, see the UMCS (Upper Memory Chip Select Register)
reference in the processor User’s manual.
outport(0xffa0, 0x80bf); // UMCS, 512K ROM, 0x80000-0xfffff
Initialize LCS (Lower Chip Select) for use with the SRAM. It is configured so that:
Address space starts 0x00000, with a maximum of 512K RAM.
Three wait state operation. Reducing this value can improve performance.
Disables PSRAM, and disables need for external ready.
outport(0xffa2, 0x7fbf); // LMCS, base Mem address 0x0000
Initialize MMCS and MPCS so that MCS0 and PCS0-PCS6 (except for PCS4) are configured so:
MCS0 is mapped also to a 256K window at 0x80000. If used with MemCard, this
chip select line is used for the I/O window.
Sets up PCS5-6 lines as chip-select lines, with three wait state operation.
outport(0xffa8, 0xa0bf); // s8, 3 wait states
outport(0xffa6, 0x81ff); // CS0MSKH
Initialize PACS so that PCS0-PCS3 are configured so that:
Sets up PCS0-3 lines as chip-select lines, with fifteen wait state operation.
The chip select lines starts at I/O address 0x0000, with each successive chip select line addressed
0x100 higher in I/O space.
outport(0xffa4, 0x007f); // CS0MSKL, 512K, enable CS0 for RAM
Configure the two PIO ports for default operation. All pins are set up as default input, except for P12
(used for driving the LED), and peripheral function pins for SER0 and SER1, as well as chip
selects for the PPI.
outport(0xff78,0xe73c);
//
PDIR1,
TxD0,
RxD0,
TxD1,
RxD1,
// P16=PCS0, P17=PCS1=PPI
outport(0xff76,0x0000);
// PIOM1
outport(0xff72,0xec7b);
// PDIR0, P12,A19,A18,A17,P2=PCS6=RTC
outport(0xff70,0x1000);
// PIOM0, P12=LED
Configure the PPI 82C55 to all inputs, except for lines I20-23 which are used as output for the ADC.
You can reset these to inputs if not being used for that function.
outportb(0x0103,0x9a);
// all pins are input, I20-23 output
outportb(0x0100,0);
