Chapter 3: Hardware
CAN-Engine
3-2
c:\tern\186\rom\ae86\EE40_115.hex,
c:\tern\186\rom\ae86\EE80_115.hex,
c:\tern\186\rom\ae86\EE84_115.hex.
The EE40_115.hex will run the R8820 at 40 MHz, and the EE80_115.hex will run the R1120 at 80 MHz.
The EE84_115.hex will run the R1120 at 40 MHz
By default, the EE40_115.hex is pre-programmed for the 40 MHz CAN-Engine.
User can use software to setup the CPU speed:
outport(0xfff8,0x0103); // PLLCON, 20MHz crystal, 0103=40 MHz, 0107=80MHz
3.2.2
External Interrupts and Schmitt Trigger Input Buffer
There are eight external interrupts: INT0-INT6 and NMI.
/INT0, J2 pin 8, free to use.
/INT1, J2 pin 6, free to use.
INT2, J2 pin 19, RTC DS1337 alarm
/INT3, J2 pin 21, CAN
/INT4, J2 pin 33, used by 100M BaseT Ethernet
INT5=P12=DRQ0, J2 pin 5, used for LED/EE/HWD
INT6=P13=DRQ1, J2 pin 11, Free to use.
/NMI, J2 pin 7
Some of external interrupt inputs, /INT0, 1, 3, 4 and /NMI, are buffered by Schmitt-trigger inverters (U9,
74HC14), in order to increase noise immunity and transform slowly changing input signals to fast changing
and jitter-free signals. As a result of this buffering, these pins are capable of only acting as input.
These buffered external interrupt inputs require a falling edge (HIGH-to-LOW) to generate an interrupt.
The CAN-Engine uses vector interrupt functions to respond to external interrupts. Refer to the Am186ES
User’s manual for information about interrupt vectors.
3.2.3
Asynchronous Serial Ports
The Am186ES CPU has two asynchronous serial channels: SER0 and SER1. Both asynchronous serial
ports support the following:
•
Full-duplex operation
•
7-bit, 8-bit, and 9-bit data transfers
•
Odd, even, and no parity
•
One stop bit
•
Error detection
•
Hardware flow control
•
DMA transfers to and from serial ports
•
Transmit and receive interrupts for each port
•
Multidrop 9-bit protocol support
•
Maximum baud rate of 1/16 of the CPU clock speed
•
Independent baud rate generators
The software drivers for each serial port implement a ring-buffered DMA receiving and ring-buffered
interrupt transmitting arrangement. See the samples files s1_echo.c and s0_echo.c.
