Terasic TR10a-LPQ User Manual Download Page 87

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TR10a-LPQ User Manual

www.terasic.com

December

10,

2018

Figure 6-16 Screenshot of Program Menu

Type 2 followed by a ENTERY key to select Link Info item. The PICe link information
will be shown as in

Figure 6-17

. Gen3 link speed and x8 link width are expected.

Figure 6-17 Screenshot of Link Info

Summary of Contents for TR10a-LPQ

Page 1: ...1 TR10a LPQ User Manual www terasic com December 10 2018 ...

Page 2: ... 4 Flash_Programming Example 44 3 5 Flash_Factory Example 45 3 6 Flash_User Example 47 3 7 Flash_Tool Example 48 3 8 Programming Batch File 48 3 9 Restore Factory Settings 49 Chapter 4 Peripheral Reference Design 51 4 1 Configure Si5340A in RTL 51 4 2 Nios II control for SI5340 57 Chapter 5 Memory Reference Design 60 5 1 QDRII SRAM Test 60 5 2 QDRII SRAM Test by Nios II 63 Chapter 6 PCI Express Re...

Page 3: ...3 TR10a LPQ User Manual www terasic com December 10 2018 8 1 Dashboard Connected via USB Blaster II 110 8 2 Dashboard Connected via UART 116 Additional Information 128 Getting Help 128 ...

Page 4: ...he Arria 10 GX FPGA features integrated transceivers that transfer at a maximum of 12 5 Gbps allowing the TR10a LPQ to be fully compliant with version 3 0 of the PCI Express standard as well as allowing an ultra low latency straight connections to two external 40G QSFP modules Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy...

Page 5: ...ive parallel FPPx16 configuration via MAX II CPLD and flash memory General user input output 4 LEDs 2 push buttons 2 dip switches Clock System 50MHz Oscillator Programmable clock generators Si5340A and Si53306 Memory QDRII SRAM FLASH Communication Ports Two QSFP connectors Dual PCI Express PCIe x8 edge connector One 2x5 GPIO timing expansion header System Monitor and Control Temperature sensor Fan...

Page 6: ...am Figure 1 1 shows the block diagram of the TR10a LPQ board To provide maximum flexibility for the users all key components are connected to the Arria 10 GX FPGA device Thus users can configure the FPGA to implement any system design Figure 1 1 Block diagram of the TR10a LPQ board Below is more detailed information regarding the blocks in Figure 1 1 Arria 10 GX FPGA 10AX115N2F45E1SG 1 150K logic ...

Page 7: ... CPLD System Controller and Fast Passive Parallel FPP x16 configuration Memory devices 40MB QDRII SRAM 128MB FLASH General user I O 4 user controllable LEDs 2 user push buttons 2 user dip switches On Board Clock 50MHz oscillator Programming PLL providing clock for 40G QSFP transceiver Programming PLL providing clock for PCIe transceiver Programming PLL providing clocks for QDRII SRAM Four QSFP por...

Page 8: ...anual www terasic com December 10 2018 System Monitor and Control Temperature sensor Fan control Power monitor UART to USB for board management Power Source PCI Express 4 pin DC 12V power PCI Express edge connector power ...

Page 9: ... the TR10a LPQ 2 1 Board Overview Figure 2 1 and Figure 2 2 are the top and bottom view of the TR10a LPQ development board It depicts the layout of the board and indicates the location of the connectors and key components Users can refer to this figure for relative location of the connectors and key components Figure 2 1 FPGA Board Top T ...

Page 10: ...r up For programming by on board USB Blaster II the following procedures show how to download a configuration bit stream into the Arria 10 GX FPGA Make sure that power is provided to the FPGA board Connect your PC to the FPGA board using a micro USB cable and make sure the USB Blaster II driver is installed on PC Launch Quartus Prime programmer and make sure the USB Blaster II is detected In Quart...

Page 11: ...nce LED Name Description D10 12 V Power Illuminates when 12 V power is active D9 3 3 V Power Illuminates when 3 3 V power is active D6 LED_MAX_CONF_DONE Illuminates when the FPGA is successfully configured Driven by the MAX 10 CPLD System Controller D8 LED_MAX_LOAD Illuminates when the MAX 10 CPLD System Controller is actively configuring the FPGA Driven by the MAX 10 CPLD System Controller with t...

Page 12: ...s when the temperature of the FPGA is too high and exceeds the set value the FPGA power is automatically turned off D1 JTAG_LED Indicates transmit or receive activity of the JTAG chain The LED flickers if the link is in use and active D2 FAN_ALERT_n Illuminates when the temperature of the FPGA exceeds the set value Setup PCI Express Control DIP switch The PCI Express Control DIP switch S1 is provi...

Page 13: ... Off Disable dual x8 presence detect On Setup Configure Mode The position 1 3 of DIP switch S1 are used to specify the configuration mode of the FPGA As currently only one mode is supported please set all positions as shown in Figure 2 5 Figure 2 5 Position of DIP switch S1 for Configure Mode Select Flash Image for Configuration The position 4 of DIP switch S1 is used to specify the image for conf...

Page 14: ...ut Output This section describes the user I O interface to the FPGA User Defined Push buttons The FPGA board includes four user defined push buttons that allow users to interact with the Arria 10 GX device Each push button provides a high logic level or a low logic level when it is not pressed or pressed respectively Table 2 3 lists the board references signal names and their corresponding Arria 1...

Page 15: ...ia 10 GX Pin Number PB0 BUTTON0 High Logic Level when the button is not pressed 1 8 V PIN_AR6 PB1 BUTTON1 1 8 V PIN_AP6 PB4 CPU_RESET_n 1 8 V AP24 User Defined Dip Switch There are two dip switches on the FPGA board to provide additional FPGA input control When a dip switch is in the DOWN position or the UPPER position it provides a high logic level or a low logic level to the Arria 10 GX FPGA res...

Page 16: ...0 High logic level when SW in the UPPER position 1 8 V PIN_ AU35 SW1 1 8 V PIN_AH33 User Defined LEDs The FPGA board consists of 4 user controllable LEDs to allow status and debugging signals to be driven to the LEDs from the designs loaded into the Arria 10 GX device Each LED is driven directly by the Arria 10 GX FPGA The LED is turned on or off when the associated pins are driven to a low or hig...

Page 17: ... V PIN_W11 LED3 LED3 1 8 V PIN_V10 2 4 Temperature Sensor and Fan Control The TR10a LPQ has an automatic management system for the temperature of the FPGA the fan speed and the power supply of the FPGA As shown in Figure 2 11 The MAX10 FPGA is the main control device on the board The temperature of the Arria 10 FPGA is obtained through the TMP441 temperature sensor and the MAX10 FPGA can read it f...

Page 18: ... temperature Figure 2 11 The Temperature Fan Speed and FPGA power control system 2 5 Power Monitor The TR10a LPQ has implemented a power monitor chip to monitor the board input power voltage and current Figure 2 12 shows the connection between the power monitor chip and the Arria 10 GX FPGA The power monitor chip monitors both shunt voltage drops and board input power voltage allows user to monito...

Page 19: ...tion I O Standard Arria 10 GX Pin Number POWER_MONITOR_I2C_SCL Power Monitor SCL 1 8V PIN_AT26 POWER_MONITOR_I2C_SDA Power Monitor SDA 1 8V PIN_AP25 POWER_MONITOR_ALERT_N Power Monitor ALERT 1 8V PIN_BD23 2 6 Clock Circuit The development board includes four 50 MHz oscillators and two programmable clock generators Figure 2 13 shows the default frequencies of on board all external clocks going to t...

Page 20: ...A and Si5340B to generate 40G Ethernet QSFP and high bandwidth memory reference clocks respectively Table 2 7 lists the clock source signal names default frequency and their corresponding Arria 10 GX device pin numbers Table 2 7 Clock Source Signal Name Default Frequency Pin Assignments and Functions Source Schematic Signal Name Default Frequency I O Standard Arria 10 GX Pin Number Application U38...

Page 21: ...k for C port QDRIID_REFCLK_p 275 MHz LVDS PIN_BB18 QDRII reference clock for D port Table 2 8 lists the programmable oscillator control pins signal names I O standard and their corresponding Arria 10 GX device pin numbers Table 2 8 Programmable oscillator control pin Signal Name I O standard Pin Assignments and Descriptions Programmable Oscillator Schematic Signal Name I O Standard Arria 10 GX Pin...

Page 22: ... V CPLD System Controller Figure 2 14 shows the connections between the Flash MAX and Arria 10 GX FPGA Figure 2 14 Connection between the Flash Max and Arria 10 GX FPGA Table 2 9 lists the flash pin assignments signal names and functions Table 2 9 Flash Memory Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Arria 10 GX Pin Number FLASH_A1 Address...

Page 23: ...Address bus 1 8 V PIN_AT6 FLASH_A22 Address bus 1 8 V PIN_AR9 FLASH_A23 Address bus 1 8 V PIN_AB13 FLASH_A24 Address bus 1 8 V PIN_AF12 FLASH_A25 Address bus 1 8 V PIN_AT9 FLASH_A26 Address bus 1 8 V PIN_AV8 FLASH_A27 Address bus Reserve 1 8 V PIN_AB12 FLASH_D0 Data bus 1 8 V PIN_AN11 FLASH_D1 Data bus 1 8 V PIN_AT12 FLASH_D2 Data bus 1 8 V PIN_AP8 FLASH_D3 Data bus 1 8 V PIN_AT11 FLASH_D4 Data bu...

Page 24: ...read and write data ports with DDR signaling at up to 550 MHz Table 2 10 Table 2 11 Table 2 12 Table 2 13 and Table 2 14 lists the QDRII SRAM Bank A B C D and E pin assignments signal names relative to the Arria 10 GX device in respectively Table 2 10 QDRII SRAM A Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Arria 10 GX Pin Number QDRIIA_A0 Ad...

Page 25: ...us 2 1 8 V HSTL Class I PIN_E13 QDRIIA_D3 Write data bus 3 1 8 V HSTL Class I PIN_B13 QDRIIA_D4 Write data bus 4 1 8 V HSTL Class I PIN_E11 QDRIIA_D5 Write data bus 5 1 8 V HSTL Class I PIN_C12 QDRIIA_D6 Write data bus 6 1 8 V HSTL Class I PIN_B12 QDRIIA_D7 Write data bus 7 1 8 V HSTL Class I PIN_A12 QDRIIA_D8 Write data bus 8 1 8 V HSTL Class I PIN_D11 QDRIIA_D9 Write data bus 9 1 8 V HSTL Class ...

Page 26: ...STL Class I PIN_L14 QDRIIA_Q17 Read Data bus 17 1 8 V HSTL Class I PIN_M12 QDRIIA_BWS_n0 Byte Write select 0 1 8 V HSTL Class I PIN_C10 QDRIIA_BWS_n1 Byte Write select 1 1 8 V HSTL Class I PIN_E8 QDRIIA_K_P Clock P Differential 1 8 V HSTL Class I PIN_F12 QDRIIA_K_N Clock N Differential 1 8 V HSTL Class I PIN_E12 QDRIIA_CQ_P Echo clock P 1 8 V HSTL Class I PIN_J13 QDRIIA_CQ_N Echo clock N 1 8 V HST...

Page 27: ...17 1 8 V HSTL Class I PIN_L17 QDRIIB_A18 Address bus 18 1 8 V HSTL Class I PIN_K17 QDRIIB_A19 Address bus 19 1 8 V HSTL Class I PIN_H17 QDRIIB_A20 Address bus 20 1 8 V HSTL Class I PIN_H18 QDRIIB_A21 Address bus 21 1 8 V HSTL Class I PIN_K18 QDRIIB_D0 Write data bus 0 1 8 V HSTL Class I PIN_C18 QDRIIB_D1 Write data bus 1 1 8 V HSTL Class I PIN_G19 QDRIIB_D2 Write data bus 2 1 8 V HSTL Class I PIN_...

Page 28: ...1 QDRIIB_Q11 Read Data bus 11 1 8 V HSTL Class I PIN_F22 QDRIIB_Q12 Read Data bus 12 1 8 V HSTL Class I PIN_E22 QDRIIB_Q13 Read Data bus 13 1 8 V HSTL Class I PIN_C21 QDRIIB_Q14 Read Data bus 14 1 8 V HSTL Class I PIN_A22 QDRIIB_Q15 Read Data bus 15 1 8 V HSTL Class I PIN_E23 QDRIIB_Q16 Read Data bus 16 1 8 V HSTL Class I PIN_B22 QDRIIB_Q17 Read Data bus 17 1 8 V HSTL Class I PIN_C22 QDRIIB_BWS_n0...

Page 29: ...I PIN_N32 QDRIIC_A11 Address bus 11 1 8 V HSTL Class I PIN_M32 QDRIIC_A12 Address bus 12 1 8 V HSTL Class I PIN_T31 QDRIIC_A13 Address bus 13 1 8 V HSTL Class I PIN_R31 QDRIIC_A14 Address bus 14 1 8 V HSTL Class I PIN_K38 QDRIIC_A15 Address bus 15 1 8 V HSTL Class I PIN_L37 QDRIIC_A16 Address bus 16 1 8 V HSTL Class I PIN_K36 QDRIIC_A17 Address bus 17 1 8 V HSTL Class I PIN_N33 QDRIIC_A18 Address ...

Page 30: ...ead Data bus 3 1 8 V HSTL Class I PIN_G32 QDRIIC_Q4 Read Data bus 4 1 8 V HSTL Class I PIN_J31 QDRIIC_Q5 Read Data bus 5 1 8 V HSTL Class I PIN_G34 QDRIIC_Q6 Read Data bus 6 1 8 V HSTL Class I PIN_L31 QDRIIC_Q7 Read Data bus 7 1 8 V HSTL Class I PIN_L30 QDRIIC_Q8 Read Data bus 8 1 8 V HSTL Class I PIN_J30 QDRIIC_Q9 Read Data bus 9 1 8 V HSTL Class I PIN_P28 QDRIIC_Q10 Read Data bus 10 1 8 V HSTL C...

Page 31: ...8 V HSTL Class I PIN_AV17 QDRIID_A4 Address bus 4 1 8 V HSTL Class I PIN_AU15 QDRIID_A5 Address bus 5 1 8 V HSTL Class I PIN_AV15 QDRIID_A6 Address bus 6 1 8 V HSTL Class I PIN_BA15 QDRIID_A7 Address bus 7 1 8 V HSTL Class I PIN_BA16 QDRIID_A8 Address bus 8 1 8 V HSTL Class I PIN_AY17 QDRIID_A9 Address bus 9 1 8 V HSTL Class I PIN_BA17 QDRIID_A10 Address bus 10 1 8 V HSTL Class I PIN_AW16 QDRIID_A...

Page 32: ...D_D15 Write data bus 15 1 8 V HSTL Class I PIN_AM14 QDRIID_D16 Write data bus 16 1 8 V HSTL Class I PIN_AJ14 QDRIID_D17 Write data bus 17 1 8 V HSTL Class I PIN_AK14 QDRIID_Q0 Read Data bus 0 1 8 V HSTL Class I PIN_BA14 QDRIID_Q1 Read Data bus 1 1 8 V HSTL Class I PIN_BB13 QDRIID_Q2 Read Data bus 2 1 8 V HSTL Class I PIN_BC13 QDRIID_Q3 Read Data bus 3 1 8 V HSTL Class I PIN_BC10 QDRIID_Q4 Read Dat...

Page 33: ... I PIN_AV13 Table 2 14 QDRII SRAM E Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Arria 10 GX Pin Number QDRIIE_A0 Address bus 0 1 8 V HSTL Class I PIN_BD30 QDRIIE_A1 Address bus 1 1 8 V HSTL Class I PIN_BD31 QDRIIE_A2 Address bus 2 1 8 V HSTL Class I PIN_AY28 QDRIIE_A3 Address bus 3 1 8 V HSTL Class I PIN_AY29 QDRIIE_A4 Address bus 4 1 8 V HST...

Page 34: ...e data bus 8 1 8 V HSTL Class I PIN_AM32 QDRIIE_D9 Write data bus 9 1 8 V HSTL Class I PIN_AP31 QDRIIE_D10 Write data bus 10 1 8 V HSTL Class I PIN_AR31 QDRIIE_D11 Write data bus 11 1 8 V HSTL Class I PIN_AT31 QDRIIE_D12 Write data bus 12 1 8 V HSTL Class I PIN_AV32 QDRIIE_D13 Write data bus 13 1 8 V HSTL Class I PIN_AU32 QDRIIE_D14 Write data bus 14 1 8 V HSTL Class I PIN_AU33 QDRIIE_D15 Write da...

Page 35: ... HSTL Class I PIN_AL32 QDRIIE_K_n Clock N Differential 1 8 V HSTL Class I PIN_AL31 QDRIIE_CQ_p Echo clock P 1 8 V HSTL Class I PIN_AL32 QDRIIE_CQ_n Echo clock N 1 8 V HSTL Class I PIN_AL31 QDRIIE_RPS_n Report Select 1 8 V HSTL Class I PIN_BC27 QDRIIE_WPS_n Write Port Select 1 8 V HSTL Class I PIN_BB27 QDRIIE_DOFF_n PLL Turn Off 1 8 V HSTL Class I PIN_BA27 QDRIIE_ODT On Die Termination Input 1 8 V ...

Page 36: ...annel 1 1 4 V PCML PIN_AY5 QSFPA_TX_P2 Transmitter data of channel 2 1 4 V PCML PIN_BB1 QSFPA_RX_P2 Receiver data of channel 2 1 4 V PCML PIN_BA3 QSFPA_TX_P3 Transmitter data of channel 3 1 4 V PCML PIN_AY1 QSFPA_RX_P3 Receiver data of channel 3 1 4 V PCML PIN_AW3 QSFPA_MOD_SEL_n Module Select 1 8V PIN_AL36 QSFPA_RST_n Module Reset 1 8V PIN_AN37 QSFPA_SCL 2 wire serial interface clock 1 8V PIN_AV3...

Page 37: ...eivers on the Arria 10 GX device it is able to provide a fully integrated PCI Express compliant solution for multi lane x1 x4 and x8 applications With the PCI Express hard IP block incorporated in the Arria 10 GX device it will allow users to implement simple and fast protocol as well as saving logic resources for logic application Figure 2 16 presents the pin connection established between the Ar...

Page 38: ...T44 PCIE_TX_p2 Add in card transmit bus 1 4 V PCML PIN_AP44 PCIE_TX_p3 Add in card transmit bus 1 4 V PCML PIN_AM44 PCIE_TX_p4 Add in card transmit bus 1 4 V PCML PIN_AK44 PCIE_TX_p5 Add in card transmit bus 1 4 V PCML PIN_AH44 PCIE_TX_p6 Add in card transmit bus 1 4 V PCML PIN_AF44 PCIE_TX_p7 Add in card transmit bus 1 4 V PCML PIN_AD44 PCIE_RX_p0 Add in card receive bus 1 4 V PCML PIN_AU42 PCIE_...

Page 39: ...d transmit bus 1 4 V PCML PIN_M44 PCIE2_TX_p2 Add in card transmit bus 1 4 V PCML PIN_K44 PCIE2_TX_p3 Add in card transmit bus 1 4 V PCML PIN_H44 PCIE2_TX_p4 Add in card transmit bus 1 4 V PCML PIN_F44 PCIE2_TX_p5 Add in card transmit bus 1 4 V PCML PIN_D44 PCIE2_TX_p6 Add in card transmit bus 1 4 V PCML PIN_B44 PCIE2_TX_p7 Add in card transmit bus 1 4 V PCML PIN_A42 PCIE2_RX_p0 Add in card receiv...

Page 40: ...S422 and external clock inputs UART applications Table 2 18 shows the mapping of the FPGA pin assignments to the 2x5 GPIO header Figure 2 17 Pin out of Timing Expansion Header Table 2 18 Timing Expansion Header Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Stratix 10 GX SX Pin Number GPIO_P0 Bi direction 1 8V GPIO 1 8 V PIN_W13 GPIO_P1 Bi direc...

Page 41: ...s the procedure to enable the FPGA configuration from Flash Users can select one boot image between factory image and user image 1 Make sure the two default FPGA configurations data has been stored in the CFI flash 2 Set the FPGA configuration mode to FPPx16 mode by setting S1 MSEL 2 0 as 000 as shown in Figure 3 1 3 Specify the configuration of the FPGA using the default Factory Configuration Ima...

Page 42: ...h MAX V CPLD and Stratix 10 GX FPGA can access this Flash device MAXV CPLD accesses flash for FPP x16 configuration of the FPGA at power on and board reset events It uses the PFL II Mega function Arria10 10 GX FPGA access to the flash memory s user space is done by Nios II Table 3 1 shows the memory map for the on board flash This memory provides non volatile storage for two FPGA bit streams and N...

Page 43: ... the MAX V CPLD can know where to find the FPGA configuration data If developers erase all flash content please ensure that the PFL option is reprogrammed with the FPGA configuration data For user s application the User hardware must be stored with start address 0x02B40000 and the user s software is suggested to be stored with start address 0x05E40000 Users also can overwrite the Factory hardware ...

Page 44: ...h_User are simple designs with Nios II processor These two designed are written into CFI Flash so they are selected to configure the FPGA when the FPGA is powered on Figure 3 3 Relationship between three flash examples The Flash_Tool is designed to show how to access flash via the Nios II processor The design shows how to erase flash and read flash content 3 4 Flash_Programming Example The Flash_P...

Page 45: ...the FPGA board is shipped To develop this kind of boot code first developers need to include the Tri State Conduit Bridge and the Generic Tri State Controller in the Platform Designer formerly Qsys to implement the flash controller function and connect the Nios II processor s data bus and instruction bus to the flash controller as shown in Figure 3 6 Then specify the Factory Software Location 0x05...

Page 46: ...46 TR10a LPQ User Manual www terasic com December 10 2018 Figure 3 6 Flash Controller Settings in Platform Designer formerly Qsys Figure 3 7 Factory Software Reset Vector Settings for NIOS II Processor ...

Page 47: ...ata and Nios II code are stored in the User Hard area and User Software area when the FPGA board is shipped The major difference between the Flash_User and Flash_Factory is the Reset Vector address in the Nios II processor component and the LED control code in Nios II program The User Software Location 0x05E40000 is used as Reset Vector as shown in Figure 3 9 Figure 3 9 User Software Reset Vector ...

Page 48: ...guration Read Serial Number from the CFI Flash Erase Serial Number to the CFI flash Erase option bits used by FPP x16 Erase whole flash 3 8 Programming Batch File The Flash_Restore folder includes batch files to program the Factory image and User image into the CFI flash Figure 3 11 shows the contents of the Flash_Restore folder The factory subfolder includes the sof elf files generated by the Fla...

Page 49: ...ion bit into a single file flash pof 3 Use jtagconfig utility to adjust jtag speed 4 Use quartus_pgm utility to program flash with flash pof Developers can copy their sof efl files into the factory folder or the user folder and launch the flash_program bat to program their code into the CFI Flash 3 9 Restore Factory Settings This section describes how to restore the original Factory image and User...

Page 50: ...ORY_LOAD dip in S1 4 to the 1 position 4 Power on the FPGA Board and the Configure Done LED D4 should light up The batch file converts the Factory and User sof elf and PFL option bit into a flash pof file and use Quartus Programmer to program the CFI Flash with the generated flash pof The factory subfolder includes Flash_Programming sof and NIOS_APP elf files generated by Flash_Factory project and...

Page 51: ...5340A in RTL There is a Silicon Labs Si5340A clock generators on TR10a LPQ FPGA board can provide adjustable frequency reference clock See Figure 4 1 for QSFP connectors and memory modules QDR II The Si5340A clock generator can output four differential frequencies from 100Hz 712 5Mhz though I2C interface configuration This chapter will show you how to use FPGA RTL IP to configure each Si5340A PLL ...

Page 52: ...Quartus top project See Figure 4 2 Figure 4 2 The controller IP of the Si5340A Using Si5340A control IP Table 4 1 lists the instruction ports of Si5340A Controller IP Table 4 1 Si5340A Controller Instruction Ports Port Direction Description iCLK input System Clock 50Mhz iRST_n input Synchronous Reset 0 Module Reset 1 Normal iStart input Start to Configure positive edge ...

Page 53: ...n fill in the input ports iXCVR0_REF_CLK iXCVR1_REF_CLK and iMEM0_REF_CLK with desired frequency values and recompile the project For example in the components Si5340A change iXCVR0_REFCLK XCVR_REF_644M53125 to iXCVR0_REFCLK XCVR_REF_322M265625 Recompile project the Si5340A OUT0 channel for QSFP output frequency will change from 644 53125Mhz to 322 26562Mhz Table 4 2 Si5340A Controller Reference C...

Page 54: ...ntrol IP built in frequencies are not users desired users can refer to the below steps to the modify control IP register parameter settings to modify the IP to output a desired frequency 1 Firstly download ClockBuilder Pro Software See Figure 4 3 which is provided by Silicon Labs This tool can help users to set the Si5340A s output frequency of each channel through the GUI interface and it will au...

Page 55: ...m December 10 2018 Figure 4 3 ClockBuilder Pro Wizard 2 After the installation select Si5340 and configure the input frequency and output frequency as shown in Figure 4 4 Figure 4 4 Define Output Clock Frequencies on ClockBuilder Pro Wizard ...

Page 56: ...sers setting frequency corresponding register value See Figure 4 5 Figure 4 5 Open Design Report on ClockBuilder Pro Wizard 4 Open Si5340A control IP sub module si5340a_i2c_reg_controller v as shown in Figure 4 6 refer Design Report parameter to modify sub module corresponding register value See Figure 4 7 Figure 4 6 Sub Module file si5340a_i2c_reg_controller v ...

Page 57: ... modify clock constrain setting in SDC file 4 2 Nios II control for SI5340 This demonstration shows how to use the Nios II processor to program the programmable oscillators Si5340A on the FPGA board System Block Diagram Figure 4 8 shows the system block diagram of this demonstration The system requires a 50 MHz clock provided from the board Si5340A is controlled by Nios II through the PIO controll...

Page 58: ...ld be followed with the choice number Figure 4 9 Menu of Demo Program In the external PLL Si5340A programming test the program will program the PLL first and subsequently will use TERASIC QSYS custom CLOCK_COUNTER IP to count the clock count in a specified period to check whether the output frequency is changed as configured To avoid a Quartus Prime compilation error dummy transceiver controllers ...

Page 59: ... and Instructions Make sure Quartus Prime 18 0 and Nios II EDS are installed on your PC Power on the TR10a LPQ board Use the USB Cable to connect your PC and the FPGA board and install USB Blaster II driver if necessary Execute the demo batch file test bat under the batch file folder NIOS_BASIC_DEMO demo_batch After the Nios II program is downloaded and executed successfully a prompt message will ...

Page 60: ...nable you to maximize memory bandwidth with separate read and write ports The memory architecture features separate read and write ports operating twice per clock cycle to deliver a total of four data transfers per cycle The resulting performance increase is particularly valuable in bandwidth intensive and low latency applications This demonstration utilizes five QDRII SRAMs on the FPGA board It d...

Page 61: ...stration each QDRII SRAM has its own PLL DLL and OCT resources The Arria 10 EMIF QDRII IP uses a Hard PHY and a soft Controller The Hard PHY capable of performing key memory interface functionality such as read write leveling FIFO buffering to lower latency and improve margin timing calibration and on chip termination The Avalon bus read write test RW_test modules read and write the entire memory ...

Page 62: ...d QDRII_x5_Test_550MHz sof Demonstration Batch File Demo Batch File Folder QDRII_x5_Test_550MHz demo_batch The demo batch files include the followings Batch file for USB Blaster II test bat FPGA configuration file QDRII_x5_Test_550MHz sof Demonstration Setup Make sure Quartus Prime Standard 18 0 and Nios II EDS are installed on your PC Connect the USB cable to the FPGA board and host PC Install th...

Page 63: ...e QDRII SRAM controller handles the complex aspects of using QDRII SRAM by initializing the memory devices managing SRAM banks and keeping the devices refreshed at appropriate intervals System Block Diagram Figure 5 2 shows the system block diagram of this demonstration The QSYS system requires one 50 MHz and five 550MHz clock source The five 550MHz clock source is provided by Si5340A clock genera...

Page 64: ...rification The program will show progress in JTAG Terminal when writing reading data to from the SRAM When verification process is completed the result is displayed in the JTAG Terminal Design Tools Quartus Prime Standard 18 0 Nios II Eclipse 18 0 Demonstration Source Code Quartus Project directory NIOS_QDRII_x5_550 Nios II Eclipse NIOS_QDRII_x5_550 software Nios II Project Compilation Nios II Pro...

Page 65: ...ard 18 0 and Nios II 18 0 are installed on your PC Make sure both QDRII SRAMs are installed on the FPGA board Power on the FPGA board Use USB Cable to connect PC and the FPGA board and install USB Blaster II driver if necessary Execute the demo batch file test bat under the folder NIOS_QDRII_x5_550 demo_batch After Nios II program is downloaded and executed successfully a prompt message will be di...

Page 66: ...66 TR10a LPQ User Manual www terasic com December 10 2018 Figure 5 3 Progress and Result Information for the QDRII Demonstration ...

Page 67: ...Hard IP for PCI Express with Avalon MM DMA IP is used in this demonstration For detail about this IP please refer to Altera document ug_a10_pcie_avmm_dma pdf 6 1 PCI Express System Infrastructure Figure 6 1 shows the infrastructure of the PCI Express System in this demonstration It consists of two primary components FPGA System and PC System The FPGA System is developed based on Arria 10 Hard IP f...

Page 68: ...nstrations PCIe_SW_KIT folder which includes PCI Express Driver PCI Express Library PCI Express Examples The kernel mode driver assumes the PCIe vender ID VID is 0x1172 and the device ID DID is 0xE003 If different VID and DID are used in the design users need to modify the PCIe vender ID VID and device ID DID in the driver INF file accordingly The PCI Express Library is implemented as a single DLL...

Page 69: ...the read and write operations are specified under the hardware design on the FPGA 6 3 PCI Express Software Stack Figure 6 2 shows the software stack for the PCI Express application software on 64 bit Windows The PCI Express driver incorporated in the DLL library is called TERASIC_PCIE_AVMM dll Users can develop their applications based on this DLL The altera_pcie_win_driver sys kernel driver is pr...

Page 70: ... steps below 1 Install the TR10a LPQ on the PCIe slot of the host PC 2 Make sure Altera Programmer and USB Blaster II driver are installed 3 Execute test bat in CDROM Demonstrations PCIe_Fundamental demo_batch to configure the FPGA 4 Restart windows operation system 5 Click Control Panel menu from Windows Start menu Click Hardware and Sound item before clicking the Device Manager to launch the Dev...

Page 71: ...ate Driver Software dialog 6 In the How do you want to search for driver software dialog click Browse my computer for driver software item as shown in Figure 6 4 Figure 6 4 Dialog of Browse my computer for driver software 7 In the Browse for driver software on your computer dialog click the Browse ...

Page 72: ...here altera_pcie_din_driver inf is located as shown in Figure 6 5 Click the Next button Figure 6 5 Browse for driver software on your computer 8 When the Windows Security dialog appears as shown Figure 6 6 click the Install button Figure 6 6 Click Install in the dialog of Windows Security ...

Page 73: ...asic com December 10 2018 9 When the driver is installed successfully the successfully dialog will appears as shown in Figure 6 7 Click the Close button Figure 6 7 Click Close when the installation of Altera PCI API Driver is complete ...

Page 74: ...es the following files TERASIC_PCIE_AVMM h TERASIC_PCIE_AVMM DLL 64 bit DLL Below lists the procedures to use the SDK files in users C C project 1 Create a 64 bit C C project 2 Include TERASIC_PCIE_AVMM h in the C C project 3 Copy TERASIC_PCIE_AVMM DLL to the folder where the project exe is located 4 Dynamically load TERASIC_PCIE_AVMM DLL in C C program To load the DLL please refer to the PCIe fun...

Page 75: ...matched card index a zero based index based on the matched verder ID and device ID Return Value Return a handle to presents specified PCIe card A positive value is return if the PCIe card is opened successfully A value zero means failed to connect the target PCIe card This handle value is used as a parameter for other functions e g PCIE_Read32 Users need to call PCIE_Close to release handle once t...

Page 76: ...e return by PCIE_Open function PcieBar Specify the target BAR PcieAddress Specify the target address in FPGA pdwData A buffer to retrieve the 32 bit data Return Value Return TRUE if read data is successful otherwise FALSE is returned PCIE_Write32 Function Write a 32 bit data to the FPGA Board Maximal write size is 4GB 1 bytes Prototype bool PCIE_Write32 PCIE_HANDLE hPCIE PCIE_BAR PcieBar PCIE_ADDR...

Page 77: ...emory mapped memory of FPGA board in DMA Maximal read size is 4GB 1 bytes Prototype bool PCIE_DmaRead PCIE_HANDLE hPCIE PCIE_LOCAL_ADDRESS LocalAddress void pBuffer DWORD dwBufSize Parameters hPCIE A PCIe handle return by PCIE_Open function LocalAddress Specify the target memory mapped address in FPGA pBuffer A pointer to a memory buffer to retrieved the data from FPGA The size of buffer should be...

Page 78: ...a memory buffer to store the data which will be written to FPGA dwDataSize Specify the byte number of data which will be written to FPGA Return Value Return TRUE if write data is successful otherwise FALSE is returned PCIE_ConfigRead32 Function Read PCIe Configuration Table Read a 32 bit data by given a byte offset Prototype bool PCIE_ConfigRead32 PCIE_HANDLE hPCIE DWORD Offset DWORD pdwData Param...

Page 79: ... Demonstration Files Location The demo file is located in the batch folder CDROM demonstrations PCIe_fundamental demo_batch The folder includes following files FPGA Configuration File PCIe_Fundamental sof Download Batch file test bat Windows Application Software folder windows_app includes PCIE_FUNDAMENTAL exe TERASIC_PCIE_AVMM dll Demonstration Setup 1 Install the FPGA board on your PC as shown i...

Page 80: ...W_KIT PCIe_Driver 4 Restart Windows 5 Make sure the Windows has detected the FPGA Board by checking the Windows Control panel as shown in Figure 6 10 Figure 6 10 Screenshot for PCIe Driver 6 Goto windows_app folder execute PCIE_FUNDMENTAL exe A menu will appear as shown in Figure 6 11 ...

Page 81: ...ic com December 10 2018 Figure 6 11 Screenshot of Program Menu 7 Type 0 followed by a ENTERY key to select Led Control item then input 15 hex 0x0f will make all led on as shown in Figure 6 12 If input 0 hex 0x00 all led will be turn off ...

Page 82: ...l 8 Type 1 followed by an ENTERY key to select Button Status Read item The button status will be report as shown in Figure 6 13 Figure 6 13 Screenshot of Button Status Report 9 Type 2 followed by an ENTERY key to select DMA Testing item The DMA test result will be report as shown in Figure 6 14 ...

Page 83: ...tus Project Demonstrations PCIe_Fundamental Visual C Project Demonstrations PCIe_SW_KIT PCIE_FUNDAMENTAL FPGA Application Design Figure 6 15 shows the system block diagram in the FPGA system In the Qsys Altera PIO controller is used to control the LED and monitor the Button Status and the On Chip memory is used for performing DMA testing The PIO controllers and the On Chip memory are connected to ...

Page 84: ... is built by Visual C 2012 The project includes the following major files Name Description PCIE_FUNDAMENTAL cpp Main program PCIE c Implement dynamically load for TERAISC_PCIE_AVMM DLL PCIE h TERASIC_PCIE_AVMM h SDK library file defines constant and data structure The main program PCIE_FUNDAMENTAL cpp includes the header file PCIE h and defines the controller address according to the FPGA design ...

Page 85: ...en are defined in TERASIC_PCIE_AVMM h If developer change the Vender ID and Device ID and PCI Express IP they also need to change the ID value define in TERASIC_PCIE_AVMM h If the return value of PCIE_Open is zero it means the driver cannot be accessed successfully In this case please make sure The FPGA is configured with the associated bit stream file and the host is rebooted The PCI express driv...

Page 86: ... is located in the batch folder CDROM demonstrations PCIe_QDR demo_batch The folder includes following files FPGA Configuration File PCIe_QDR sof Download Batch file test bat Windows Application Software folder windows_app includes PCIE_QDR exe TERASIC_PCIE_AVMM dll Demonstration Setup 1 Install the FPGA board on your PC 2 Configure FPGA with PCIe_QDR sof by executing the test bat 3 Install PCIe d...

Page 87: ...er 10 2018 Figure 6 16 Screenshot of Program Menu 7 Type 2 followed by a ENTERY key to select Link Info item The PICe link information will be shown as in Figure 6 17 Gen3 link speed and x8 link width are expected Figure 6 17 Screenshot of Link Info ...

Page 88: ...MA On Chip Memory Test item The DMA write and read test result will be report as shown in Figure 6 18 Figure 6 18 Screenshot of On Chip Memory DMA Test Result 9 Type 4 followed by an ENTERY key to select DMA QDRII A Memory Test item The DMA write and read test result will be report as shown in Figure 6 19 ...

Page 89: ...rasic com December 10 2018 Figure 6 19 Screenshot of QDRII A Memory DAM Test Result 10 Type 5 followed by an ENTERY key to select DMA QDRII B Memory Test item The DMA write and read test result will be report as shown in Figure 6 20 ...

Page 90: ...rasic com December 10 2018 Figure 6 20 Screenshot of QDRII B Memory DAM Test Result 11 Type 6 followed by an ENTERY key to select DMA QDRII C Memory Test item The DMA write and read test result will be report as shown in Figure 6 21 ...

Page 91: ...rasic com December 10 2018 Figure 6 21 Screenshot of QDRII C Memory DAM Test Result 12 Type 7 followed by an ENTERY key to select DMA QDRII D Memory Test item The DMA write and read test result will be report as shown in Figure 6 22 ...

Page 92: ...rasic com December 10 2018 Figure 6 22 Screenshot of QDRII D Memory DAM Test Result 13 Type 8 followed by an ENTERY key to select DMA QDRII E Memory Test item The DMA write and read test result will be report as shown in Figure 6 23 ...

Page 93: ...ocation Quartus Project Demonstrations PCIE_QDR Visual C Project Demonstrations PCIe_SW_KIT PCIE_QDR FPGA Application Design Figure 6 24 shows the system block diagram in the FPGA system In the Qsys Altera PIO controller is used to control the LED and monitor the Button Status and the On Chip memory is used for performing DMA testing The PIO controllers and the On Chip memory are connected to the ...

Page 94: ...are project is built by Visual C 2012 The project includes the following major files Name Description PCIE_QDR cpp Main program PCIE c Implement dynamically load for TERAISC_PCIE_AVMM DLL PCIE h TERASIC_PCIE_AVMM h SDK library file defines constant and data structure The main program PCIE_QDR cpp includes the header file PCIE h and defines the controller address according to the FPGA design ...

Page 95: ... the PCI Express driver The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM h If developer change the Vender ID and Device ID and PCI Express IP they also need to change the ID value define in TERASIC_PCIE_AVMM h If the return value of PCIE_Open is zero it means the driver cannot be accessed successfully In this case please make sure The FPGA is co...

Page 96: ...www terasic com December 10 2018 The memory mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API as shown below The pcie link information is implemented by PCIE_ConfigRead32 API as shown below ...

Page 97: ...Ie Bifurcation Demonstration Files Location The demo file is located in the batch folder CDROM demonstrations PCIe_funcdamental_x2 demo_batch The folder includes following files FPGA Configuration File PCIe_Fundamental_x2 sof Download Batch file test bat Windows Application Software folder windows_app includes PCIE_FUNDAMENTAL exe TERASIC_PCIE_AVMM dll Demonstration Setup 1 Make sure your Host PC ...

Page 98: ...nshot of two FPGA PCIe devices are detected Figure 6 26 Screenshot of Program Menu 8 Type 0 followed by a ENTERY key to select PCIe0 Led Control item then input 15 hex 0x0f will make all User LED lighten as shown in Figure 6 27 If input 0 hex 0x00 all User LED will be turn off ...

Page 99: ...pe 1 followed by an ENTERY key to select PCIe0 Button Status Read item The button status will be report as shown in Figure 6 28 Figure 6 28 Screenshot of PCIe0 Button Status Report 10 Type 2 followed by an ENTERY key to select PCIe0 DMA Testing item The DMA test result will be report as shown in Figure 6 29 ...

Page 100: ...Y key to select PCIe1 Led Control item then input 15 hex 0x0f will make all Bracket LED on as shown in Figure 6 30 If input 0 hex 0x00 all Bracket LED will be turn off Figure 6 30 Screenshot of PCIe1 LED Control 12 Type 4 followed by an ENTERY key to select PCIe1 Button Status Read item The button status will be report as shown in Figure 6 31 ...

Page 101: ...ort 13 Type 2 followed by an ENTERY key to select PCIe1 DMA Testing item The DMA test result will be report as shown in Figure 6 32 Figure 6 32 Screenshot of PCIe0 DMA Memory Test Result 14 Type 99 followed by an ENTERY key to exit this test program Development Tools Quartus Prime Standard 18 0 Visual C 2012 ...

Page 102: ... Status and the On Chip memory is used for performing DMA testing The PIO controllers and the On Chip memory are connected to the PCI Express Hard IP controller through the Memory Mapped Interface Figure 6 33 Hardware block diagram of the Dual PCIe reference design Windows Based Application Software Design The application software project is built by Visual C 2012 The project includes the followin...

Page 103: ...nt DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM h If developers change the Vender ID and Device ID and PCI Express IP they also need to change the ID value define in TERASIC_PCIE_AVMM h The third parameter 0 and 1 in this case is used to specify the PCIe device 0 means the first device found in the PCIe bus with the given Vender ID and Device ID 1 means ...

Page 104: ...104 TR10a LPQ User Manual www terasic com December 10 2018 The memory mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API as shown below ...

Page 105: ...t Code The transceiver test code is used to verify the transceiver channels for the QSPF ports through an external loopback method The transceiver channels are verified with the data rates 10 3125 Gbps with PRBS31 test pattern 7 2 Loopback Fixture To enable an external loopback of transceiver channels one of the following two fixtures are required QSFP Cable as shown in Figure 7 1 QSFP Loopback fi...

Page 106: ...erasic com December 10 2018 Figure 7 2 QSFP Loopback Fixture Figure 7 3 shows the FPGA board with one QSFP cable installed Figure 7 4 shows the FPGA board with two QSFP loopback fixtures installed Figure 7 3 One QSFP Cables Installed ...

Page 107: ...nsure that the FPGA board is NOT powered on 3 Plug in the QSPF loopback fixtures 4 Connect your FPGA board to your PC with a mini USB cable 5 Power on the FPGA board 6 Execute test bat in the Transceiver_Test folder under your local disk 7 The batch file will download sof and elf files and start the test immediately The test result is shown in the Nios Terminal as shown in Figure 7 5 8 To terminat...

Page 108: ...108 TR10a LPQ User Manual www terasic com December 10 2018 Figure 7 5 QSFP Transceiver Loopback Test in Progress Figure 7 6 QSFP Transceiver Loopback Done ...

Page 109: ...us to the Host PC via JTAG or UART bus The reported status includes FPGA Board temperature fan speed FPGA core power and 12V input power Figure 8 1 shows the block diagram of the TR10a LPQ Dashboard In the host PC there are two Dashboard GUI software are provided One is UART based software it can be used in Windows system Another is JTAG based software it can be used both in Windows and Linux It i...

Page 110: ...m Console tool is built in Quartus software so the Quartus software should be installed before using the Dashboard GUI based on System Console USB Blaster II Driver The Dashboard GUI based on System Console allows the Host PC connect to the TR10a LPQ board via JTAG interface so users need to install USB Blaster II driver on Host PC Dashboard GUI Tool It is Dashboard GUI main program users can find...

Page 111: ...hown in Figure 8 2 the System Console window appears As shown in Figure 8 3 click the TR10a LPQ Board Monitor System it will show the main monitor GUI such as LED status FPGA and board temperature The details will be described below Figure 8 2 System Console Window Figure 8 3 TR10a LPQ Board Monitor System Sheet ...

Page 112: ...PGA Status As shown in Figure 8 4 it indicates the TR10a LPQ status LED number For these LEDs function please refer to Table 2 1 in section 2 2 Figure 8 4 FPGA Status Section Version It will show the version of the TR10a LPQ board and the code in the system controller MAX 10 as shown in Figure 8 5 ...

Page 113: ...ashboard GUI will real time show the fan speed TR10a LPQ board ambient and FPGA temperature Users can know the board temperature in time The information will be refreshed per 0 5 second and displays through diagram and number as shown in Figure 8 6 Figure 8 7 and Figure 8 8 Figure 8 6 Temperature Fan Section ...

Page 114: ...emperature GUI Figure 8 8 Fan Speed GUI Power Monitor It will show the 12V 0 9V real time voltage current and power consumption of the TR10a LPQ board as shown in Figure 8 9 Figure 8 9 Power Monitor Section FPGA Power Down It is a board protection function provided by the system ...

Page 115: ...e board In this case the FPGA_PDN LED will be light on as shown in Figure 8 10 Users need to press the MAX_RTS button or restart the power to remove this status Figure 8 10 FPGA_PDN LED Status Log File Besides show the board status in real time it will restore the data with csv format document to the log folder in the same directory of test bat as shown in Figure 8 11 and Figure 8 12 Figure 8 11 C...

Page 116: ...information such as voltage temperature and fan speed The UART based Dashboard GUI only supports windows OS at present The usage preparation and installation details are described as below Software and Tools Installed on Host PC Install USB to UART driver Connect the board to the host PC through the USB to UART connector The driver should be installed users can find it in the Tool folder in the bo...

Page 117: ...le Please note that the system console based and UART based Dashboard GUI are use the same USB Blaster II connector The USB HUB on the board can process the USB signal Install Driver When connect the TR10a LPQ board to the host PC users also need to install USB to UART driver besides the USB Blaster II driver As shown in Figure 8 13 one USB to UART device is shown in PC Device Manager Figure 8 13 ...

Page 118: ...118 TR10a LPQ User Manual www terasic com December 10 2018 Figure 8 14 Install USB to UART driver Figure 8 15 The USB to UART device after driver is installed successfully Run Dashboard GUI ...

Page 119: ...detail functions as below Figure 8 16 UART based Dashboard GUI Dashboard GUI function introduction Start Stop As shown in Figure 8 17 there is a Start button at the bottom left of the GUI window Click it to run the program Start will change to Stop it will show the TR10a LPQ board status Users can press Stop button to stop the status data transmission and display Reset Button Press this button to ...

Page 120: ... www terasic com December 10 2018 Figure 8 17 Start and Reset button FPGA Status As shown in Figure 8 18 it will show the status LED number on the TR10a LPQ board For these LEDs function please refer to Table 2 1 in section 2 2 ...

Page 121: ...section FPGA Board Temperature The Dashboard GUI will real time show the fan speed TR10a LPQ board ambient and FPGA temperature Users can know the board temperature in time The information will be refreshed per 0 5 second and displays through diagram and number as shown in Figure 8 19 ...

Page 122: ...122 TR10a LPQ User Manual www terasic com December 10 2018 Figure 8 19 Temperature section Fan RPM It displays the real time speed of the fan on the TR10a LPQ board as shown in Figure 8 20 ...

Page 123: ...er Manual www terasic com December 10 2018 Figure 8 20 FAN RPM section 12V Core Power monitor It displays the real time 12V Core Power 0 9V voltage and consumption current on the TR10a LPQ board as shown in Figure 8 21 ...

Page 124: ...r 10 2018 Figure 8 21 Power Monitor Section Sampling Speed It can change interval time that the Dashboard GUI sample the board status Users can adjust it to 1s 10s 1min Full Speed 0 1s to sample the board status as shown in Figure 8 22 and Figure 8 23 ...

Page 125: ...Sampling Speed section Figure 8 23 Options of Sampling Speed Board Information There is a File page on the upper left of the Dashboard GUI program window click the Board Information to get the current software version and the TR10a LPQ board version as shown in Figure 8 24 ...

Page 126: ...24 Board Information Log File On the upper left of the Dashboard GUI program window click the Export in the File page to save the board temperature fan speed and voltage data in csv format document as shown in Figure 8 25 and Figure 8 26 Figure 8 25 Export the log file ...

Page 127: ...127 TR10a LPQ User Manual www terasic com December 10 2018 Figure 8 26 Export the log file in csv format ...

Page 128: ... are the addresses where you can get help if you encounter problems Terasic Technologies 9F No 176 Sec 2 Gongdao 5th Rd East Dist HsinChu City Taiwan 30070 Email support terasic com Web www terasic com TE10a HL Web TR10a LPQ terasic com Revision History Date Version Changes 2018 11 First publication ...

Page 129: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Terasic P0562 ...

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