33
C) Press and release user_pb[2]
11) To Flip XAUI Lanes
A) Set USER_DIPSW[7:0] = [00000100] (Program MDIO to flip XAUI lanes)
B) Press and release user_pb[1]
C) Press and release user_pb[2]
12) Set pre-emphasis (for example, if using an SFP+ 12 meter cable)
A) USER_DIPSW[7:0] = [11100110]
B) Press and release user_pb[1]
C) Press and release user_pb[2]
13) Press and release cpu_resetn
14) LEDs 15-8 will display the "heartbeat" pattern, indicating the FPGA fabric is functional.
15) LED 0 and 4 should be ON and LEDs 1-3 and 5-7 should be OFF.
16) Press and release user_pb[0] (Start Test)
17) LEDs 0-2 and 4-6 should all be ON and LEDs 3 and 7 should be OFF.
18) Unplug the cable from any SFP port.
19) LEDs 3 and 7 should turn ON.
NOTE: If the test doesn't pass for example with the 12 meter SFP cable, it is ok to try different
settings of
USER_DIPSW[7:3] in step 12 above to make the test pass.
To test the daughter card LEDs, observe they follow LEDs 15-8 on the host board in step 8 above.
Pressing user_pb[0] reverses the color of USER LEDS 0-3 on the daughtercard
Pressing user_pb[1] reverses the color of USER LEDS 4-7 on the daughtercard
MDIO Functionality Check
1) Open the Quartus II “hsmc_loopback.qar” file
2) After completing one of the test designs above, open the signal tap design.
a. With the “hsmc_loopback.qar” project open, locate the signal tap file named
“hsmc_loopback_sfp2_mdio.stp” (or possibly hsmc_loopback_sfp3_mdio.stp). This file can be
found under the “Files” tab in the Project Navigator window within Quartus II.
b. Make sure the JTAG is setup
3) Set USER_DIPSW[7:0] = [XXXX0111] to read back chip rev, chip ID, and microcode ID
4) In the upper left tool bar in Signaltap click on the “Run Anaylsis” button
5) Press and release user_pb[1]
6) Press and release user_pb[2]
7) Scroll to the net named *|mdio_read_data_w.
8) Zoom in to view the values and find the value of 8727h.
