13
60
PCMULK1
LVTTL
PMD CMU Lock Detect Channel 1.
120
PCMULK2
LVTTL
PMD CMU Lock Detect Channel 2.
72
PHYRESET
LVTTL
PHY Reset, Active low.
66
PLOSB1
LVTTL
PMD Loss of Signal Channel 1.
126
PLOSB2
LVTTL
PMD Loss of Signal Channel 2.
77
PRTAD01
CMOS
Channel 1 PHY Address LSB.
79
PRTAD02
CMOS
Channel 2 PHY Address LSB
73
PRTAD1
CMOS
PHY Address bit 1.
71
PRTAD2
CMOS
PHY Address bit 2.
67
PRTAD3
CMOS
PHY Address bit 3.
65
PRTAD4
CMOS
PHY Address bit 4.
47
SCK1
LVTTL
SPI ROM Clock for channel 1.
107
SCK2
LVTTL
SPI ROM Clock for channel 2.
50
SER_BOOT
LVTTL
SPI ROM Boot Enable active high.
53
SFP_TXDIS1
LVTTL,
Open drain
Optical Transmitter Enable channel 1.
113
SFP_TXDIS2
LVTTL,
Open drain
Optical Transmitter Enable channel 2.
48
SMBSPDSEL1
LVTTL
2-wire Speed Select channel 1.
108
SMBSPDSEL2
LVTTL
2-wire Speed Select channel 2.
119
SMBWEN
LVTTL
2-wire Write Enable,
49
SS_N1
LVTTL
SPI ROM Chip Select channel 1.
109
SS_N2
LVTTL
SPI ROM Chip Select channel 2.
74
TXONOFF1
CMOS
Transmit Driver On or Off channel 1.
134
TXONOFF2
CMOS
Transmit Driver On or Off channel 2.
32
XAUI_RX_1N0
Differential
CML
XAUI Parallel Receive Data Output Channel
1, lane D, negative leg.
28
XAUI_RX_1N1
Differential
CML
XAUI Parallel Receive Data Output Channel
1, lane C, negative leg.
24
XAUI_RX_1N2
Differential
CML
XAUI Parallel Receive Data Output Channel
1, lane B, negative leg.
20
XAUI_RX_1N3
Differential
CML
XAUI Parallel Receive Data Output Channel
1, lane A, negative leg.
30
XAUI_RX_1P0
Differential
CML
XAUI Parallel Receive Data Output Channel
1, lane D, positive leg.
26
XAUI_RX_1P1
Differential
CML
XAUI Parallel Receive Data Output Channel
1, lane C, positive leg.
22
XAUI_RX_1P2
Differential
CML
XAUI Parallel Receive Data Output Channel
1, lane B, positive leg.
18
XAUI_RX_1P3
Differential
CML
XAUI Parallel Receive Data Output Channel
1, lane A, positive leg.