31
7) Press and release cpu_resetn (S2).
8) Press and release user_pb[0] -- the rx is now ready to search for a prbs seed pattern
9) Press and release both cpu_resetn, user_pb[1] and user_pb[2] simultaneously
- Resets the BCM8727C device and the + SFP module(s)
10) Reset Module (It should be OK to skip this one, but include these steps if your board is failing)
A) Set USER_DIPSW[7:0] = [00000000] (Program MDIO to reset module)
B) Press and release user_pb[1]
C) Press and release user_pb[2]
11) To Flip XAUI Lanes
A) Set USER_DIPSW[7:0] = [00000100] (Program MDIO to flip XAUI lanes)
B) Press and release user_pb[1]
C) Press and release user_pb[2]
12) Set pre-emphasis (for example, if using an SFP+ 12 meter cable)
A) USER_DIPSW[7:0] = [11100110]
B) Press and release user_pb[1]
C) Press and release user_pb[2]
13) Press and release cpu_resetn
14) LEDs 15-8 will display the "heartbeat" pattern, indicating the FPGA fabric is functional.
15) LED 0 and 4 should be ON and LEDs 1-3 and 5-7 should be OFF.
16) Press and release user_pb[0] (Start Test)
17) LEDs 0-2 and 4-6 should all be ON and LEDs 3 and 7 should be OFF.
18) Unplug the RX optical cable from the channel 1 SFP port.
19) LED 3 should turn ON.
20) Unplug the TX optical cable from the channel 1 SFP port.
21) LED 7 should turn ON.
NOTE: If the test doesn't pass for example with the 12 meter SFP cable, it is ok to try different
settings of USER_DIPSW[7:3] in step 12 above to make the test pass.
To test the daughter card LEDs, observe they follow LEDs 15-8 on the host board in step 8 above.
Pressing user_pb[0] reverses the color of USER LEDS 0-3 on the daughtercard
Pressing user_pb[1] reverses the color of USER LEDS 4-7 on the daughtercard
XAUI to SFP+ Module 10G Channel-to-Channel Electrical Loopback
This design tests the dual XAUI to SFI interface using the Stratix IV GX FPGA Dev Kit platform.
The Stratix IV GX transmits 3.125G XAUI signals on the four lanes of channel 1 and the return
signal is received on channel 2. Also, the Stratix IV GX transmits 3.125G XAUI signals on the four
lanes of channel 2 and the return signal is received on channel 1. The Stratix IV GX FPGA sends a
3.125G XAUI signal on four transmit lanes from channel 1 to the BCM8727 device, which then
outputs a 10G signal to the SFP+ module on channel 1. With an SFP+ module coax electrical cable
installed such as the
Amphenol part number SF-SFPP2EPASS-002 or SFSFPP2EPASS- 012
, as
shown in
, the SFP+ sends an electrical 10G signal from SFP+ channel 1 output to SFP+
