Terasic Altera Dual-XAUI, User Manual

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J4 SFP_TXDIS1 LVTTL,
Open
drain Optical Transmitter Enable channel 1.
J12 SFP_TXDIS2 LVTTL,
Open
drain Optical Transmitter Enable channel 2.
F9 SMBSCL1 LVTTL,
Open
drain Serial Clock channel 1.
F11 SMBSCL2 LVTTL,
Open
drain Serial Clock channel 2.
F8 SMBSDA1 LVTTL,
Open
drain Serial Data channel 1.
F10 SMBSDA2 LVTTL,
Open
drain Serial Data channel 2.
K8 SMBSPDSEL1 LVTTL 2-wire Speed Select channel 1.
J15 SMBSPDSEL2 LVTTL 2-wire Speed Select channel 2.
F7 SMBWEN LVTTL 2-wire Write Enable,
L5 SS_N1 LVTTL SPI ROM Chip Select channel 1.
N11 SS_N2 LVTTL SPI ROM Chip Select channel 2.
K13 TRSTB LVTTL JTAG Test Reset pin, JTAG interface not used
for this design.
F6 TXONOFF1 CMOS Transmit Driver On or Off channel 1.
E12 TXONOFF2 CMOS Transmit Driver On or Off channel 2.
A1 XAUI_RX_1N0 Differential
CML XAUI Parallel Receive Data Output Channel
1, lane D, negative leg.
A3 XAUI_RX_1N1 Differential
CML XAUI Parallel Receive Data Output Channel
1, lane C, negative leg.
A5 XAUI_RX_1N2 Differential
CML XAUI Parallel Receive Data Output Channel
1, lane B, negative leg.
A7 XAUI_RX_1N3 Differential
CML XAUI Parallel Receive Data Output Channel
1, lane A, negative leg.
B1 XAUI_RX_1P0 Differential
CML XAUI Parallel Receive Data Output Channel
1, lane D, positive leg.
B3 XAUI_RX_1P1 Differential
CML XAUI Parallel Receive Data Output Channel
1, lane C, positive leg.
B5 XAUI_RX_1P2 Differential
CML XAUI Parallel Receive Data Output Channel
1, lane B, positive leg.
B7 XAUI_RX_1P3 Differential XAUI Parallel Receive Data Output Channel