Terasic Altera Dual-XAUI User Manual Download Page 14

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XAUI_RX_2N0

Differential
CML

XAUI Parallel Receive Data Output Channel
2, lane D, negative leg.

XAUI_RX_2N1

Differential
CML

XAUI Parallel Receive Data Output Channel
2, lane C, negative leg.

XAUI_RX_2N2

Differential
CML

XAUI Parallel Receive Data Output Channel
2, lane B, negative leg.

XAUI_RX_2N3

Differential
CML

XAUI Parallel Receive Data Output Channel
2, lane A, negative leg.

XAUI_RX_2P0

Differential
CML

XAUI Parallel Receive Data Output Channel
2, lane D, positive leg.

XAUI_RX_2P1

Differential
CML

XAUI Parallel Receive Data Output Channel
2, lane C, positive leg.

XAUI_RX_2P2

Differential
CML

XAUI Parallel Receive Data Output Channel
2, lane B, positive leg.

XAUI_RX_2P3

Differential
CML

XAUI Parallel Receive Data Output Channel
2, lane A, positive leg.

XAUI_TX_1N0

Differential
CML

XAUI Parallel Transmit Data Input Channel
1, lane D, negative leg.

XAUI_TX_1N1

Differential
CML

XAUI Parallel Transmit Data Input Channel
1, lane C, negative leg.

XAUI_TX_1N2

Differential
CML

XAUI Parallel Transmit Data Input Channel
1, lane B, negative leg.

XAUI_TX_1N3

Differential
CML

XAUI Parallel Transmit Data Input Channel
1, lane A, negative leg.

XAUI_TX_1P0

Differential
CML

XAUI Parallel Transmit Data Input Channel
1, lane D, positive leg.

XAUI_TX_1P1

Differential
CML

XAUI Parallel Transmit Data Input Channel
1, lane C, positive leg.

XAUI_TX_1P2

Differential
CML

XAUI Parallel Transmit Data Input Channel
1, lane B, positive leg.

XAUI_TX_1P3

Differential
CML

XAUI Parallel Transmit Data Input Channel
1, lane A, positive leg.

XAUI_TX_2N0

Differential
CML

XAUI Parallel Transmit Data Input Channel
2, lane D, negative leg.

XAUI_TX_2N1

Differential
CML

XAUI Parallel Transmit Data Input Channel
2, lane C, negative leg.

XAUI_TX_2N2

Differential
CML

XAUI Parallel Transmit Data Input Channel
2, lane B, negative leg.

XAUI_TX_2N3

Differential
CML

XAUI Parallel Transmit Data Input Channel
2, lane A, negative leg.

XAUI_TX_2P0

Differential
CML

XAUI Parallel Transmit Data Input Channel
2, lane D, positive leg.

Summary of Contents for Altera Dual-XAUI

Page 1: ...1...

Page 2: ...Connector 8 CHAPTER 4 COMPONENTS 17 4 1 Featured Device BCM8727 U6 17 4 2 General User Input Output 22 4 3 Clocks 23 4 4 Memory Devices 24 4 5 Power 26 CHAPTER 5 BOARD SETUP AND TEST DESIGNS 27 5 1 B...

Page 3: ...edded systems based on XAUI based Altera GX based devices At the time of this document the devices that support XAUI are Arria GX Arria II GX Stratix II GX and Stratix IV GX 3 1 1 1 1 Features Feature...

Page 4: ...Dual XAUI to SFP HSMC board 4 1 2 1 2 Getting Help Getting Help Here are some places to get help if you encounter any problem Email to support terasic com Taiwan China 886 3 550 8800 Korea 82 2 512 7...

Page 5: ...HSMC board including block diagram and components Figure 2 1 The Dual XAUI to SFP HSMC PCB and component diagram A photograph of the Dual XAUI to SFP HSMC board is shown in Figure 2 1 It depicts the...

Page 6: ...e XAUI interfaces will be attached to the HSMC side of the card and the SFI side of the interface will be attached to the SFP optical modules on the opposite side of the board The lower HSMC channels...

Page 7: ...status and configuration registers accessible through an I2C port Other signals will include loss of signal OPRXLOS 2 1 and module absent MOD_ABS 2 1 An oscillator capable of generating 156 25MHz is s...

Page 8: ...rfaces and the pin description on the Dual XAUI to SFP HSMC board 8 3 1 3 1 HSMC Expansion Connector HSMC Expansion Connector The Dual XAUI to SFP HSMC board contains a HSMC connector Figure 3 1 Figur...

Page 9: ...Figure 3 1 Pin outs of Bank 1 on the HSMC connector 9...

Page 10: ...Figure 3 2 Pin outs of Bank 2 on the HSMC connector 10...

Page 11: ...Figure 3 3 Pin outs of Bank 3 on the HSMC connector 11...

Page 12: ...Alarm Status Interrupt Channel 2 116 MDC2 CMOS Management Data Clock for single device default 114 MDIO2 CMOS Management Data Clock channel 2 for dual MDIO device 41 MISO1 LVTTL Master Input Slave Out...

Page 13: ...nnel 2 119 SMBWEN LVTTL 2 wire Write Enable 49 SS_N1 LVTTL SPI ROM Chip Select channel 1 109 SS_N2 LVTTL SPI ROM Chip Select channel 2 74 TXONOFF1 CMOS Transmit Driver On or Off channel 1 134 TXONOFF2...

Page 14: ...el Transmit Data Input Channel 1 lane C negative leg 23 XAUI_TX_1N2 Differential CML XAUI Parallel Transmit Data Input Channel 1 lane B negative leg 19 XAUI_TX_1N3 Differential CML XAUI Parallel Trans...

Page 15: ...MDC1 CMOS No Connect for single MDIO device default Management Data Clock channel 1 for dual MDIO device 54 MDIO1 CMOS No Connect for single MDIO device default Management Data I O channel 1 for dual...

Page 16: ...USER_LED_R0 CMOS User LED Red 0 89 USER_LED_R1 CMOS User LED Red 1 85 USER_LED_R2 CMOS User LED Red 2 83 USER_LED_R3 CMOS User LED Red 3 151 USER_LED_R4 CMOS User LED Red 4 149 USER_LED_R5 CMOS User...

Page 17: ...high speed front end providing the highest performance and most flexibility for line card designers An on chip microcontroller implements the control algorithm for the DSP core All signal names and B...

Page 18: ...No Connect for single MDIO device default Management Data I O channel 1 for dual MDIO device M1 NVMA1SEL LVTTL Non volatile Memory Select G9 NVMPROT CMOS Non volatile Memory Protect E10 OPINLVL LVTTL...

Page 19: ...nalog Recovered Clock from CDR Channel 2 positive leg T8 RDICM_1 Analog Receiver Common Mode Input channel 1 V18 RDICM_2 Analog Receiver Common Mode Input channel 2 K5 SCK1 LVTTL SPI ROM Clock for cha...

Page 20: ...F6 TXONOFF1 CMOS Transmit Driver On or Off channel 1 E12 TXONOFF2 CMOS Transmit Driver On or Off channel 2 A1 XAUI_RX_1N0 Differential CML XAUI Parallel Receive Data Output Channel 1 lane D negative l...

Page 21: ...Differential CML XAUI Parallel Transmit Data Input Channel 1 lane C negative leg F2 XAUI_TX_1N2 Differential CML XAUI Parallel Transmit Data Input Channel 1 lane B negative leg D2 XAUI_TX_1N3 Differen...

Page 22: ...e USER LEDs located on the HSMC These are all 2 5V LVCMOS signals Each channel has a bi colored LED The 4 states of each bi color LED Off green red orange can be used to identify received or transmitt...

Page 23: ...23 4 3 4 3 Clocks Clocks Figure 4 1 shows the XAUI to SFP HSMC board clock diagram Figure 4 1 XAUI to SFP HSMC Clocking Diagram...

Page 24: ...nterface they are connected to The board has the following memory interfaces 8K EEPROM connected to HSMC 2 x 256K SPI EEPROM connected to BCM8727 and HSMC 2 x 4K EEPROM connected to BCM8727 and SFP Th...

Page 25: ...Clock Input U14 7 U15 7 Pull up resistor to 3 3V 3 3V Hold Input Active low U14 8 U15 8 3 3V 3 3V Supply Voltage Table 4 6 4 Kbit Serial I2C EEPROM 24LC08B Pinout Board Reference Signal Name IO Standa...

Page 26: ...26 4 5 4 5 Power Power Power is supplied to the board from the 12V supply of the host board Figure 4 2 shows the power distribution Figure 4 2 Power Tree of Dual XAUI to SFP HSMC Board...

Page 27: ...in hardware 27 5 1 5 1 Board Setup Board Setup Before powering on the host board on make sure to install a shunt on J13 and J14 Then plug the HSMC board into the host board This board was designed so...

Page 28: ...installed as shown in Figure 5 1 the SFP sends an optical 10G signal onto the optical fiber which is looped back into the SFP optical input The SFP module converts the 10G optical signal into an elec...

Page 29: ...s for example if using an SFP 12 meter cable A USER_DIPSW 7 0 11100110 B Press and release user_pb 1 C Press and release user_pb 2 13 Press and release cpu_resetn 14 LEDs 15 8 will display the heartbe...

Page 30: ...al into an electrical 10G signal and sends it to the BCM8727 PHY The PHY then converts the 10G signal into four 3 125G XAUI output signals and transmits them on channel 2 to the Stratix IV GX device t...

Page 31: ...D 3 should turn ON 20 Unplug the TX optical cable from the channel 1 SFP port 21 LED 7 should turn ON NOTE If the test doesn t pass for example with the 12 meter SFP cable it is ok to try different se...

Page 32: ...ansmit and receive at the same time 1 Set USER_DIPSW 7 0 00000100 Flip XAUI Lanes 2 Plug in the Dual XAUI to SFP HSMC into the HSMA port on the Stratix IV GX FPGA development 3 Plug in SFP modules int...

Page 33: ...3 in step 12 above to make the test pass To test the daughter card LEDs observe they follow LEDs 15 8 on the host board in step 8 above Pressing user_pb 0 reverses the color of USER LEDS 0 3 on the da...

Page 34: ...Figure 5 4 Signal Tap Display 34...

Page 35: ...Appendix 35 6 1 6 1 Revision History Revision History Version Change Log V1 0 Initial Version Preliminary 6 2 6 2 Copyright Statement Copyright Statement Copyright 2010 Terasic Technologies All rights...

Page 36: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Terasic P0092...

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