Telink TLSR8232 BLE SDK Developer Handbook
AN-19112700-E1
178
Ver.1.0.0
10.1.8 PWM Phase
void
pwm_set_phase
(
pwm_id
id,
unsigned
short
phase)
is used to set delay
time before PWM is started.
“phase” is the delay time, the unit is the number of PWM
clocks. Generally it can be set as 0 (no delay).
10.1.9 PWM Interrupt
Some basic concepts about Telink MCU interrupt are introduced here.
Interrupt “status” is state flag bit generated by hardware interrupt request of certain IRQ
source, and it does not depend on software setting. No matter whether “mask” is
enabled, interrupt request will always set corresponding IRQ “status” to 1. Generally,
“status” can be cleared to 0 by writing it with “1”.
Interrupt response: When CPU receives an interrupt request (IRQ) from certain IRQ
source, it will determine whether to respond to the IRQ. If yes, firmware pointer PC will
jump to interrupt handling part “irq_handler”.
To enable
interrupt response, please make sure all “mask” bits corresponding to current
IRQ are enabled. One IRQ may correspond to multiple “mask” bits which are the relation
of logic “And”. IRQ request won’t trigger interrupt response unless all of its related “mask”
bits are enabled.
PWM driver in the “register.h” only involves the following IRQ sources.
#define
reg_pwm_irq_mask
REG_ADDR8(0x7b0)
#define
reg_pwm_irq_sta
REG_ADDR8(0x7b1)
enum
{
FLD_IRQ_PWM0_PNUM
=
BIT(0),
FLD_IRQ_PWM0_IR_DMA_FIFO_DONE
=
BIT(1),
FLD_IRQ_PWM0_FRAME
=
BIT(2),
FLD_IRQ_PWM1_FRAME
=
BIT(3),
FLD_IRQ_PWM2_FRAME
=
BIT(4),
FLD_IRQ_PWM3_FRAME
=
BIT(5),
FLD_IRQ_PWM4_FRAME
=
BIT(6),
FLD_IRQ_PWM5_FRAME
=
BIT(7),
};
The eight IRQ sources listed in the enum c
orrespond to core_7b0 BIT<0:7> (“mask”) /
core_7b1 BIT<0:7> (“status”).
In the figure below, PWM0 works in IR mode, duty cycle of Signal Frame is 50%, pulse
number (i.e. Signal Frame number) for each IR task is 3. This figure will help to illustrate
the
three types for PWM IRQ “status”.