Teledyne Kibra DDR, User Manual, Page: 22 / 174

Teledyne LeCroy DDR Interposer
20 Kibra DDR Protocol Analyzer User Manual
1.5.4 External Trigger In
Edge detected. (Rising edge only)
Voltage required:
Signal needs to be > 800mV to see a logic "1"
Signal needs to be < 400mV to see a logic "0"
Accumulated Latency from SMA terminal to Recognition in FPGA: 70 ns (+/ ‐ 10 ns).
Always active in Manual or Event Trigger mode, no additional software setting is
required. An input voltage of is 540mV +/ ‐ 100 will cause a trigger condition which will be
identified in the trace file. The latency on this trigger is approximately 120 ns.
1.5.5 Low Latency Read/Write Trigger Out
The low ‐ latency SMA trigger out ports on the front of the analyzer operate continuously
on Read/Write operations. The pulse occurs as soon as the Kibra 380 or Kibra 480
interposer is powered on. The analyzer SW does not need to be actively recording. The
settings in the recording options tab have no effect on the low ‐ latency SMA trigger out
feature.
The Read/Write trigger out ports on the front of the analyzer generate a very short pulse
width of about 1.25 ns (for 800 MHz DDR3) and relatively low amplitude of 560 mVp ‐ p
(after 1 ‐ m cable). This trigger out signaling differs from the LVTTL Trigger out on the back
of the analyzer in order to shorten the cycle time when triggering on back ‐ to ‐ back Read
or Write operations.
This trigger out signaling is designed to allow the end user to initiate an acquisition on an
oscilloscope and then use the trigger marker in the waveform to correlate transmission
of the read or write commands with the actual DQ/DQS signals. The R/W trigger out
latency is dependent on the signaling frequency:
At DIMM Clock = 800 MHz/1600MTs: Delay is about 39.2 ns.
At DIMM Clock = 667 MHz/1333MTs: Delay is about 42.2 ns.
At DIMM Clock = 533 MHz/1066MTs: Delay is about 47.4 ns.
*Plus the 2ns per foot for the SMA cable length