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Teledyne
LeCroy
Supplemental
Timing
Information
164
Kibra
DDR
Protocol
Analyzer
User
Manual
5.1.47
V48 - tXS-FAST SRX to a Valid Command with DLL - DDR4
Defined
as
the
interval
between
Self
Refresh
Exit
command
and
the
next
Valid
command
that
needs
DLL.
tXS
‐
FAST
is
defined
as
tXS_FAST
=
tRFC4(min)
+
10ns
5.2
Supplemental Timing Information
5.2.1
tWR WR (write recovery for auto-precharge)
tWR
specifies
the
minimum
interval
between
the
last
burst
write
cycle
and
the
point
where
the
precharge
command
can
be
issued
to
the
same
bank.
Speed
Grade
800
1066
1333
1600
1866
Min
(ns)
15
15
15
15
15
Summary of Contents for Kibra DDR
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