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Teledyne
LeCroy
DDR3
and
DDR4
JEDEC
Timing
Violations
Summary
160
Kibra
DDR
Protocol
Analyzer
User
Manual
5.1.22
V22 - tddWTW WRITE to WRITE delay (different rank, same DIMM)
Defined
as
the
interval
between
a
WRITE
command
and
the
next
Write
command
to
a
different
rank
in
same
DIMM.
Timing
between
commands
to
a
different
rank
should
be
vendor
specified.
5.1.23
V23 - tddWTW WRITE to WRITE delay (different DIMM)
Defined
as
the
interval
between
a
WRITE
command
and
the
next
Write
command
to
different
DIMM.
Timing
between
commands
to
a
different
rank
or
DIMM
should
be
vendor
specified.
5.1.24
V24 - tXS SELF REFRESH EXIT to a Valid Command (without DLL)
Defined
as
the
interval
between
Self
Refresh
Exit
command
and
the
next
Valid
command
that
doesn’t
need
DLL.
Exiting
Self
‐
Refresh
(SRX)
is
transmitted
by
a
combination
of
CKE
high
plus
NOP
/
Deselect
command.
A
delay
of
at
least
tXS
(5nCK,
tRFC(min)+10ns)
must
be
satisfied
before
a
valid
command
(not
requiring
a
locked
DLL)
can
be
issued.
This
is
to
allow
completion
of
any
internal
refresh
operations
in
progress.
5.1.25
V25 - tXSDLL SELF REFRESH EXIT to a Valid Command (with DLL)
Defined
as
the
interval
between
Self
Refresh
Exit
command
and
the
next
Valid
command
that
needs
DLL.
Exiting
Self
‐
Refresh
(SRX)
requires
combination
of
CKE
high
plus
NOP
/
Deselect
command
asserted
for
at
least
2
CKs.
Before
a
command
that
requires
a
locked
DLL
can
be
applied,
a
delay
of
at
least
tXSDLL
(512
CKs)
and
applicable
ZQCAL
function
requirements
(TBD)
must
be
satisfied.
5.1.26
V26 - tCKESR SELF REFRESH ENTRANCE to SELF REFRESH EXIT
Defined
as
the
minimum
interval
between
Self
Refresh
entrance
and
Self
Refresh
Exit.
At
Self
Refresh
Entry,
CKE
must
be
low
plus
the
NOP
/
Deselect
command
asserted
for
at
least
2CKs
followed
by
Self
Refresh
exit
where
CKE
must
be
high
plus
the
NOP
/
Deselect
command
asserted
for
at
least
CKE
+
1.
5.1.27
V27 - tACTPDEN ACTIVE to POWER DOWN ENTRY
Defined
as
the
interval
between
Active
command
and
initiating
Power
down
entry.
Active
can
be
issued
one
clock
prior
to
initiating
PDE
for
all
speed
bins.
5.1.28
V28 - REFPDEN REFRESH to POWER DOWN ENTRY
Defined
as
the
interval
between
Refresh
command
and
initiating
Power
down
entry.
Refresh
can
be
issued
one
clock
prior
to
initiating
PDE
for
all
speed
bins.
Summary of Contents for Kibra DDR
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