Theory of Operation
Main Board
Serial Digital Input
Processing
The serial digital circuitry receives the SDI input streams after they have been
equalized, from either the SDI I/O board or the PHY3 board, depending on the
installed options. The SDI streams are passed to the DSP FPGAs where they
undergo measurement and raster processing. The signal information is then passed
to the DSY FPGA for picture processing, recursion, and display combining. The
result is shown on the external DVI-I connector.
Reference Input
The Reference input is a passive loopthrough, which is AC coupled and buffered.
Operation varies, depending on whether the instrument is operating in digital
or composite input mode. For digital inputs the reference signal is applied to a
sync separator whose output is supplied to the DSP FPGA, where the timing
information is derived. For composite inputs, the reference signal is routed to the
Option CPS composite input board, where a 10-bit ADC digitizes the signal. The
digitized signal is then routed back to the DSP FPGA on the main board so the
timing information can be derived, as with the digital process.
Digital Waveform
Processing Engine
The data streams from the Composite and SDI video inputs are applied to the
waveform processing FPGA. This block deformats, up-samples, interpolates,
demodulates, and otherwise processes the data to generate the signals needed
to create the displays.
Rasterizing Engine
The Rasterizer engine resides in the same DSP FPGA as the waveform processing
engine. This block builds up the variable intensity images in the fast static RAM.
For each pixel of the display, the Rasterizer Engine increments the intensity of that
pixel every time the waveform hits its coordinates. As a result the waveform areas
hit more frequently are brighter. For any given frame, the intensity map is built up
in one memory chip and read out of the other. The functions swap on the next
fi
eld.
Recursion and Picture
Processing Engine
The output of the rasterizer feeds the picture and recursive processing engine
in the second large FPGA. This engine adds the previous frame to the present
frame to reduce
fl
icker and improve brightness. It also converts the picture and
waveform signals from the input rate of 50 or 59.94 Hz to 60 Hz frame rate to
work with the DVI-I monitor. The picture and waveform data combine with the
graphics and audio bar information from the control processor, and then output
to the XGA DAC to drive the external monitor. Note that the parallel data from
the serial digital inputs connect directly to this FPGA to provide the picture
functionality, bypassing the waveform processing engine.
Control Processor
The control processor is in charge of all the operational modes in the instrument.
It draws the audio bars, communicates with the front panel, and controls most
other internal devices though either the SPI or the I
2
C bus. Audio data is input to
the control processor via the 8 bit HPI bus.
WVR7200 Waveform Rasterizer Service Manual
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