Specifications
3–12
TMS 420 R3051, R3052 & R3081 Microprocessor Support Instruction Manual
In Custom clocking, the module clocking state machine (CSM) generates one
master sample for each microprocessor bus cycle, no matter how many clock
cycles are contained in the bus cycle.
Figure 3–3 shows the sample points and the master sample point.
Most R3051 signals are acquired on the falling edge of SYSCLK. The nine
signals that do not become active at that time are hardware latched and shifted to
the falling edge shown in Figure 3–3.
SYSCLK~
ALE
RDCEN~ or ACK~
Address Lines
A/D(31–4)
ADDR (1–0)
Diag_0
Diag_1
Rd~
Reset~
Addr (2–3)
BE_3~ (A/D(3))
BE_2~ (A/D(2))
BE_1~ (A/D(1))
BE_0~ (A/D(0))
Hardware latched
on probe adapter
Ack~
RdCEn~
BusError”
Data
Sysclk_B”
ALE_B
INT_D”
BUS Gnt~
Brst~_WrNr~
Figure 3–3: R3051, R3052 and R3081 bus timing with a probe adapter
If you choose to use Without Probe Adapter, both edges of Sysclk_B~ are used
for clocking. Therefore, there is no need for hardware latches. The effect is lower
clock speed support. Figure 3–4 shows the timing when not using the probe
adapter.