Theory of
Operation—MicroLab
|
Instruction
What
happens
is
basically this:
If
you
want
to break on a
specific
address,
you
first
must store the
address
in
the
breakpoint
address
latch.
An
|/O
address
is
sent
to
the
Latch
Address
Decoder. The
decoder enables the address
latch to
store the
low-order eight bits
and
high-order eight
bits
of
the address
from
data bus
lines
BDO-BD7.
The
stored
address values are then constantly compared
with
the address present
on
AO-A15
from
the
personality
card.
If
amatch
occurs,
the comparator issues the
ADDR
=
signal.
To
further
qualify
the
match,
you
can set
up an exclusive
OR
comparator
to
detect
whether
the
address was
an
|/O
or
memory
access,
and
if
a
read
or
write
was
performed.
This
is
done
by
loading
a
0,1
latch with
the
specific
values
that
will
tell
you
if
the
BR/W
line
is
high
or
low,
and
if
the
BM/IO
line
is
high
or low.
The latched
states
are then
compared
with
the
real
states
of
the
control lines.
You
can
also qualify
a
break with
the
special lines (SPO-SP5) from
the
personality card.
For example,
if
you
want
to break on
areadtoan!/O
portat
address
C400,
you
would
load
the
0,1 Latch
with
a
O
for
BR/W,
an
1
for
BM/IO,
and
load
C400
into
the address
latch.
When
this
condition occurs, a
breakpoint
interrupt
is
generated.
If
you
don’t
care
about
the
states
of
BR/W,
BM/IO,
or
the
special
lines,
you
can
program
the
Don’t
Care
Latch
with
all
1's, which
will
cause
the
breakpoint to occur only on
the
event
of
an
address
match.
Or,
you
can
selectively
set the
Don’t
Care latch to break on some, but
not
all
of
the
conditions.
Next,
we'll discuss how the
Breakpoint circuitry
is
controlled,
starting with
the
Latch
Address
Decoder.
Latch
Address Decoder
>
fH
The
Latch
Address
Decoder
is
a
3-to-8
decoder/demultiplexer
that
will
cause one
of
its
output
lines to go
low,
depending
on
the
address
input.
The Latch
Address
Decoder
is
connected
to
the
internal
bus
lines
BAO-BA3,
and
is
enabled
by
two signals:
ONBDIO
(indicating an internal I/O operation),
and
BE
(bus enable).
BAG
is
also
used as
an
enabling
signal.
When
the
personality
card
asserts
BE
and
indicates
an
internal I/O
operation
by
forcing
ONBDIO
low,
the
address
at
BAO-BA2
is
enabled
into U6010. Depending on
the
states
of
BAO-BA2,
one
of
the
five
outputs
of
U6010
will
go
low.
These outputs
control:
@
the High-Order
Address
Latch
(at
address
OB)
@
the
Low-Order
Address
Latch
(at
address
OA)
@
the
0,1 Latch (at
address
OC)
@
the
Don't Care
Latch (at
address
OD)
@
the
Breakpoint
Control Latch (at
address
OE)
As
the
breakpoint
logic
is
set
up,
each
of these
latches
is
in
turn enabled.
High-Order Address
AA
Latch/Comparator
The High-Order
Address
Latch
(U9030)
is
clocked
by
the
rising edge
of
U6010's
pin 12. At
that
time,
the
data on
BDO-BD7
is
latched
into
U9030
and
presented
to
the
‘B’
inputs
of
comparator
U9040.
BA8
and
BAY,
and A10-A15
are
brought
to
the
‘A’
inputs
of
the
comparator. When
a
match
occurs between the
‘A’
and
‘B’ inputs,
pin 19
of
U9040
goes
low. This
low
is
fed
to
the
El
input
of
the
Low-
Order comparator.
Low-Order Address
>
4A
Latch/
Comparator
The Low-Order
Address Latch/Comparator
works
in
the
same
way
as
the
High-Order
Address
Latch/Comparator.
The
desired
low-order
address
is
latched
into U7030,
then
compared
with
the
states
of BAO-BA7.
But
in
this
comparator,
the
El
input
(from
U9040)
must
be
lowbefore
a
match can occur.
When
a
match does occur,
U7040's
EO
pin
goes
low,
and
this
low
is
fed to
the
Breakpoint Enable
circuitry.
Qualifying
Logic
Now,
let’s
look
at
the
logic
that
qualifies
the address
match.
The
address
match
may
be
qualified
by
the
0,1
Latch
and
the
Don’t
Care
Latch.
Let's
look
at
the
0,1
Latch
first.
0,1
Latch.
The
0,1
Latch
works
in
combination with
the
Exclusive
OR
Comparators to qualify an
address
match.
Notice
that
U5070
has outputs
labled R/WC, M/IOC, and
SPOC-SPSC.
These
lines
decide
the states
of
the
BR/W,
BM/IO,
and
BSPO-BSP6
signals
necessary
to aquire
a
breakpoint.
For example,
if
you
wanted
to break on
an1/O
address,
you
would
place
a
1
on
pin
4
of
U5070,
then
latch
that
1
onto output
pin 5. Pin
5
of
U5070
is
tied
to pin 12
of
Exclusive
OR
Comparator
U6070
(at
the
bottom
center
of
schematic
5).
In
this
case,
you
would get a
low
out
of
pin
11
of
the
comparator
only
if
the
BM/IO
line
went
to
a
1
state
(indicating an
1/O
operation). The low out
of
pin
11
of
U6070
istied
to
pin
10
of
U6080B
of
the
Breakpoint Enable
logic. (We'll
talk
about
U6080B
later.)
Summary of Contents for 067-0892-00
Page 9: ...MicroLab Instruction 2827 1 The TEKTRONIX MicroLab I vi REV A JUN 1980...
Page 101: ......
Page 102: ...MICROLAB AlddNS Y3MOd 3YHNDIS...
Page 103: ...JANVd LNOYS Z AHNDIS MICROLAB...
Page 104: ......
Page 110: ......