On
the other
hand,
if
you
wanted
to break on
a
memory
operation, you'd place
a
O
on
pin
5
of U5O70.
Then,
the
output
of
U6070 would
go low
only
if
the
BM/IO line
went
low
(indicating
a
memory
access).
The
same
rules
stand
true
for
BR/W
and the
BSPO-BSP5
lines.
To
match
a
low
state,
a
O
is
placed into
the
appropriate
location
in
U5070.
To
match
a
high
state,
a
1
is
placed into
the appropriate
location.
Don't
Care
Latch.
Notice that
there are
eight lines coming
out
of
the
Exclusive
OR
Comparators (U4070, U6070).
There
may
be
situations
where
you'll
want
to qualify
an
address
breakpoint
with
only
a
few
of these
eight
lines.
The
Don’t
Care
Latch
is
used
to
override
some
orall
of
the
comparator outputs
by
forcing
them
low.
Suppose
you
wanted
to
break
only
if
the
BSP4
line
from
the
personality
card
was
high.
First
of all,
you would
place
a
1
on
pin 17
of
U5070,
then
latch
the
1
through
to
pin
12
of
comparator
U4070. That would
assure that
every
time the
BSP4
line
went
high,
output
pin
11
of
the comparator
would
go low. Next,
to mask out
all
other
comparisons,
except
the
address
match
of
course,
you
would place
a
0
into
pin
14
of
U5080 (the
Don’t
Care
Latch).
All
other
inputs
to
U5080 would be
1’s.
When
these
signals are
latched
through
U5080, they
are
fed to inverters U4080
and
U6090.
(Notice
that
the outputs
of
the
Exclusive
OR
Comparators
are
all
tied
to
the
outputs
of
the
inverters. The
comparators
have open-collector outputs,
and their
output
states
can be overridden
by
the
inverter outputs.)
At
this
point,
the
inverters
have
forced
all
of
the comparator
lines
low,
except the
SP4 output. When the
BSP4
line
from
the
personality
card goes high, pin
11
of
U4070
will
go
low.
If
this occurs at
the
same time
an
address
comparison
is
made,
a
breakpoint occurs. The Breakpoint
Enable
circuitry
takes
over,
and
a
breakpoint
interrupt
is
issued.
Fd
The Breakpoint Enable
logic
collects
signals
from
several
different
places,
and
determines
if
a
valid breakpoint
has
been reached.
The Breakpoint Enable
logic
is
primarily
divided
into
two
sections: a
section that determines
if
an
address
and
control
line
match
has
occurred,
and
a
section
that
determines
if
a
special
line
match
has
occured. Notice
that
NAND
gate
U6080A
(near
the
top_of
the Breakpoint
Enable
logic)
is connected
to
five
of
the
SP
outputs
from
the
Exclusive
OR
Comparators.
If
SPO-SP4
from
the
comparators are
low,
the output
of
U6080A
goes
high,
indicating
a
match.
Now,
look
at
U6080B.
You
can
see
that
U60808
is
connected
to
the
ADDR=
line,
and
to
the
M/IO
Breakpoint Enable
®
Theory of Operation—MicroLab
|
Instruction
and R/W
lines from
the
Exclusive
OR
Comparators.
In
addition, U6080B
is
connected
to
the
BE
line
from
the
personality
card,
and
to
the
output
of
the
Breakpoint
Delay
Counter
(U1070). We'll
discuss
the Breakpoint
Delay
Counter
later.
The Breakpoint Enable
logic
can
issue
a
break
if
the
output
of
U6080A
and
the
output
of
U6080B
are
high,
OR
if
either
of
their
outputs
is
high. Selection
between
the two
functions
is
controlled
by
the
ORE
signal
from
the
Breakpoint
Control
register
(U2070).
When
the
ORE
line
is
high,
either
U6080B
or
the U6080A/U2030C
combination
can
cause
a
breakpoint.
When
the
ORE
line
is
low,
an
AND
combination
must
exist
to
cause
a
breakpoint. Let's
look
at
how
this
works.
OR. The
key
devices
in
this
circuit
are
U3080D, and
U4090(A,
B,
and
C).
Let’s
assume
that
the
ORE
line from
the
Breakpoint
Control
register
is
high, indicating
that
either U6080A/U2030C
or
U6080B
can cause
a
breakpoint
to
occur. Let's
further assume that
the
breakpoint
will
come from U6080A
and
U2030C.
And
finally,
we'll
assume
that the
RCO
output
from
the
Breakpoint Delay
Counter
(U1070)
is
low,
but
will
go high
later.
(U1070
is
used
to
delay
the generation
of a
breakpoint
interrupt.
We'll talk more
about
U1070
later.)
NOTE
It
might
be
helpful
at
this
point
to
pull
out
schematic
5
and
write
down
the
states
of the various
gates we'll
talk about.
ORE
places
a
high on
pin
1
of
U4090A.
A
match
from
U6080A
puts
a
high on
pin
9 of
U2022C.
The
output
of
U2030C
is
still
low
because
RCO
is
low.
If
you follow
the
high out
of
U2022C
pin
8,
you'll
find
that
it
causes
pins 4
and
5
of
U3030B
tobe
high.
(Keep
in
mind
that
the
output
of
U6080B
is
low.)
Because
RCO
is
low,
and
is
fed to
pin
9
of
U4090C,
pin
3
of
U3030B
is
high.
All
the
inputs to U3030B
are
now
high,
causing
its
output
to be
low.
Next,
RCO
will
go to a high.
RCO
is
inverted and placed on
pin
11
of
U2030C,
allowing
pin
8 to
go high.
Nowwe
havea
high on both input pins
of
U2022C.
These
highs
force
U2022C
pin
8
low.
The
low
from
U2022C
pin
8
and the
high
from
U6030H
pin
3
are
combined at
U4090B.
The
resulting
high on
pin
6
of
U4090B
is
NANDed
with
the
high
ORE
line
to
cause
a low
on
input
pin
5
of
U3030B.
Summary of Contents for 067-0892-00
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