The option allows the
<
NumLock
>
key to be activated after system boot up.
3.3.10 Gate A20 Option
This entry allows you to select how the gate A20 is handled. The gate A20 is a device used to address
memory above 1 Mbytes. Initially, the gate A20 was handled via a pin on the keyboard (Normal). Today,
while keyboards still provide this support, it is more common, and much faster, for the system chipset
(Fast; default) to provide support for gate A20.
3.3.11 Typematic Rate Setting
Select "Enabled" to configure "Typematic Rate" and "Typematic Delay" functions.
3.3.12 Typematic Rate
Use this option to set the rate at which a character keeps repeating while you hold down a key.
3.3.13 Typematic Delay
Select "Enabled" to set the length of delay before key strokes to repeat. Available options are "250",
"500", "750", and "1000".
3.3.14 Security Option
You can select whether the password is required every time the system boots or only when you enter the
Setup. You can assign "Supervisor Password" and "User Password" in the main CMOS Setup Utility
Screen.
3.3.15 OS Select for DRAM
>
64MB
If you are using OS/2 operating system and installed memory is larger than 64MB. You need to have the
setting in the enable mode.
3.3.16 Report No FDD For WIN 95
While the FDD in " STANDARD CMOS SETUP " is set to NONE, set this option to No to release IRQ6
for passing Win95 logo. This option is irrelevant under normal operation .
3.3.17 Video BIOS Shadow
Video shadow copies BIOS code from slower ROM to faster RAM. BIOS can then execute from RAM.
3.3.18 C8000-CBFFF /DC000-DFFFF Shadow
Optional firmware will be copied from ROM to RAM. When this option is enabled.
3.4 Advanced Chipset Features Setup
These settings are intended for the Advanced Chipset function on the motherboard. Fine tuning these
options, enhances the performance of the system.
Figure 3.4 Advanced Chipset Features Screen
CMOS Setup Utility - Copyright ( C ) 1984 - 2000 Award Software
Advanced Chipset Features
DRAM Timing By SPD
Disabled
Item Help
DRAM Clock
HCLK-33M
Menu Level >
SDRAM Cycle Length
3
Bank Interleave
Disabled
Memory Hole
Disabled
P2C/C2P Concurrency
Enabled
Fast R-W Turn Around
Disabled
System BIOS Cacheable
Video BIOS Cacheable
Video RAM Cacheable
Frame Buffer Size
Enabled
Enabled
Enabled
8M
