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AD9739A-EBZ 

Quick Start Guide 

One

 Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com 

 

Getting Started with the AD9739A-EBZ Evaluation Board 

 

 

Information furnished by Analog Devices is believed to be accurate and reliable. However, no 
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other 
rights of third parties that may result from its use. Specifications subject to change without notice. No 
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 
Trademarks and registered trademarks are the property of their respective owners. 

 

 

 

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. 
Tel: 781.329.4700 

www.analog.com

  

Fax: 781.461.3113 

©2010 Analog Devices, Inc. All rights reserved. 

 

 

 

 

WHAT’S IN THE BOX 

AD9737A or AD9739A-EBZ Evaluation Board 
Evaluation Board CD 
Mini-USB Cable 

RECOMMENDED EQUIPMENT 

Low Phase Noise Sinusoidal Signal Generator or ADF4350 

Evaluation Board  

Spectrum Analyzer 
Data Pattern Generator Series 2 (DPG2)

 

 

INTRODUCTION 

The purpose of this document is to get the AD9737A or AD9739A evaluation board up and running as quickly as possible and provide 
guidance on how to optimize the controllers in the part to get the optimal performance out of the AD9737A/AD9739A. 
 

SOFTWARE 

The AD9737A/AD9739A-EBZ are designed to receive data from a DPG2. The DAC Software Suite, plus the AD9737A/AD9739A Update, 
is required for evaluation. The DAC Software Suite is included on the Evaluation Board CD, or can be downloaded from the DPG web 
site at http://www.analog.com/dpg. This will install DPGDownloader (for loading vectors into the DPG2) and the AD9737A or AD9739A 
SPI application. 
 

HARDWARE SETUP 

To operate the board, a power supply capable of +5vdc, 2A should be connected to J17.  A spectrum analyzer or an oscilloscope to view 
the DAC output should be connected to J1.  The diagram in Figure 1 shows the location of each connection.  A low jitter (< 0.5psec RMS) 
sine or square wave clock source should be connected to J3.  The DC level of the clock is unimportant since the clock is AC-coupled on 
the evaluation board before the CLKP/N inputs. The included USB cable should be used to connect the Evaluation Board to a PC. Note 
that the software described above should be installed before connecting the USB cable.  
 

 

Figure 1 

Summary of Contents for AD9739A-EBZ

Page 1: ...ocument is to get the AD9737A or AD9739A evaluation board up and running as quickly as possible and provide guidance on how to optimize the controllers in the part to get the optimal performance out of the AD9737A AD9739A SOFTWARE The AD9737A AD9739A EBZ are designed to receive data from a DPG2 The DAC Software Suite plus the AD9737A AD9739A Update is required for evaluation The DAC Software Suite...

Page 2: ...f the SPI application as shown in Figure 2 Then run the SPI application by clicking on the Run button in the upper left of the screen Figure 2 Load Pattern from the DPG2 Open DPGDownloader Start Programs Analog Devices DPG DPGDownloader Ensure that AD9737A AD9739A is selected in the Evaluation Board drop down list For this evaluation board LVDS is the only valid Port Configuration and will be sele...

Page 3: ...A buttons Click the Run button Once the run is complete the RCVR LCK and RCVR TRX ON indicators should be green as shown in Figure 9 Figure 6 Another way to verify that the controller is in the correct spot and not on the edge is to check the status of the four status bits which sample the rising edge of the DCI at four different phases DCI PHS1 should always be high and DCI PHS3 should always be ...

Page 4: ...Quick Start Guide AD9739A EBZ Rev A Page 4 of 8 Result The final result of this setup should be as shown in Figure 8 Note the RF Attenuation of 20dB to accurately measure harmonics Figure 8 ...

Page 5: ...d run the application again Controller Clock Controls and Analog FS controls The Controller Clock controls enable the Mu Controller and LVDS controllers For normal operation both of these should be enabled The Clock GEN PD switch powers down the clocking structure and should be left disabled for normal use The DAC current ouput has an adjustable full scale value The FSC Set option allows for this ...

Page 6: ...ng 0x11 Invalid Search GB sets a GB from the beginning and end of the Mu Delay line in which the Mu controller will not enter into unless it does not find a valid phase outside the GB Register 0x29 bits 0 4 Optimal value is Decimal 11 Tolerance Sets the Tolerance of the phase search Register 0x29 bit 7 0 Not Exact Can find a phase within 2 phases of the desired phase 1 Exact Finds the exact phase ...

Page 7: ...llowing bits are utilized Mu Controller Enable Register 0x26 Bit 0 Set to 0 to disable the controller MU_DEL_Manual Register 0x28 bits 0 7 and 0x27 bits 7 8 Total of 9 bits the maximum Mu delay value is d432 or x1B0 LVDS Receiver Controls Figure 14 RCV_LOOP On Register 0x10 bit 1 set to 1 RCV_ENA On Register 0x10 bit 0 set to 1 LCKTHR 2 Register 0x15 bits 0 4 RVCR_GAIN 1 Register 0x11 bit 0 set to...

Page 8: ...s are the property of their respective owners D00000 0 1 07 To ensure that the LVDS Controller is locked and tracking check the status of the following bits RCVR Lock Register 0x21 bit 0 This should be high if the controller is locked TRK_ON Register 0x21 bit 3 This should be high if the controller is tracking ...

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