D_SPEED_SEL
27
System Level Solutions
January 2013
USB 2.0 (USB20SR) Device IP Core User Guide
Value after Reset:
00h
D_SPEED_SEL
This register is used to configure the USB device core for specific speed
communication. With the use of this register, device core can be used as a
USB20 high speed device or it can be used as a USB1.1 Full speed device.
Table 4-13
shows the Device Speed Select register description.
Value after Reset:
01h
D_CNCT
This register is used to control device connect/disconnect operation through
processor. This is 8 bit register. For connection of the device with the host,
0x01 should be written to the register and to disconnect the device from host
0x00 should be written to the register.
Table 4-14
shows the Device Connect/
23:16
RO
Phy Reg Readdata
These bits are used to store readdata received from selected regis-
ter during read operation.
15:8
RW
Phy Reg writedata
These bits of the register is used to specify write data which will be
loaded inside the selected PHY register when write operation is
enabled through write_en bit setting.
7:0
RW
Phy register address
This address bits are used to select PHY chip register on which
read or write operation needs to be performed.
Table 4-13. Device Speed Select (D_SPEED_SEL) Register Details
Bit
Access
Description
7:1
RW
Reserved
0
RW
This bit is used to select speed mode for USB device IP Core.
Device can be set into high or full mode before it is connected to the
host PC.
In high speed mode, device can be attached to host in high speed if
EHCI controller is available and speed negotiation is successful
otherwise it is connected into full speed with full speed controller.
In full speed mode device can be attached to the host into full
speed only even though enhanced host controller is present.
1: Device is enabled for high speed connection
0: Device is enabled for full speed connection