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USB 2.0 (USB20SR) Device IP Core User Guide
System Level Solutions
January 2013
2. Core Architecture
The USB 2.0 Device communicates through two differential lines
(D+ & D-) that connect to a transceiver. The transceiver or physical interface,
in turn, connects to the core via interface signals. Since the core supports all
the transfer types - Control, Bulk, Isochronous and Interrupt, each transfer
type retains a separate pipe for OUT and IN operation.
Figure 2-1.
illustrates
overall architecture of the USB20SR IP core.
Figure 2-1. USB20SR Device IP Core Architecture
Each of the blocks is described in detail below:
The Micro Controller/Processor interface provides a bridge between Host
Interfaces (ex. Nios II Processor) and internal data memory and control
registers.
Protocol
Layer
ULPI
Interface
ULPI
PHY
Micro Controller /Processor Interface
(ex. AVALON BUS INTERFACE)
EndPoint
Registers
D+
D-
External
On Chip RAM
USB2.0 System Top
EP0
Controller