
12
USB 2.0 (USB20SR) Device IP Core User Guide
System Level Solutions
January 2013
Core Registers
17
EP0_BUFFER1
0x4c
32
RW
EndPoint 0 (Control Endpoint): Buffer1 Register
18
EP1_CSR
0x50
32
RW
EndPoint 1 CSR Register
19
EP1_IMS
0x54
32
RW and
ROC
EndPoint 1 Interrupt Register
20
EP1_BUFFER0
0x58
32
RW
EndPoint 1 Buffer0 Register
21
EP1_BUFFER1
0x5c
32
RW
EndPoint 1 Buffer1 Register
22
EP2_CSR
0x60
32
RW
EndPoint 2 CSR Register
23
EP2_IMS
0x64
32
ROC
EndPoint 2 Interrupt Register
24
EP2_BUFFER0
0x68
32
RW
EndPoint 2 Buffer0 Register
25
EP2_BUFFER1
0x6c
32
RW
EndPoint 2 Buffer1 Register
26
EP3_CSR
0x70
32
RW
EndPoint 3 CSR Register
27
EP3_IMS
0x74
32
ROC
EndPoint 3 Interrupt Register
28
EP3_BUFFER0
0x78
32
RW
EndPoint 3 Buffer0 Register
29
EP3_BUFFER1
0x7c
32
RW
EndPoint 3 Buffer1 Register
30
EP4_CSR
0x80
32
RW
EndPoint 4 CSR Register
31
EP4_IMS
0x84
32
ROC
EndPoint 4 Interrupt Register
32
EP4_BUFFER0
0x88
32
RW
EndPoint 4 Buffer0 Register
33
EP4_BUFFER1
0x8c
32
RW
EndPoint 4 Buffer1 Register
34
EP5_CSR
0x90
32
RW
EndPoint 5 CSR Register
35
EP5_IMS
0x94
32
ROC
EndPoint 5 Interrupt Register
36
EP5_BUFFER0
0x98
32
RW
EndPoint 5 Buffer0 Register
37
EP5_BUFFER1
0x9c
32
RW
EndPoint 5 Buffer1 Register
38
EP6_CSR
0xA0
32
RW
EndPoint 6 CSR Register
39
EP6_IMS
0xA4
32
ROC
EndPoint 6 Interrupt Register
40
EP6_BUFFER0
0xA8
32
RW
EndPoint 6 Buffer0 Register
41
EP6_BUFFER1
0xAc
32
RW
EndPoint 6 Buffer1 Register
42
EP7_CSR
0xB0
32
RW
EndPoint 7 CSR Register
Table 4-1. Register Description
Sr.
No.
Register
Offset
Width Access
Description