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USB 2.0 (USB20SR) Device IP Core User Guide

System Level Solutions
January 2013

Core Registers

TEST MODE

This register is used to configure the device into specific test mode for 

 

compliance test of the device. Different test modes are used for compliance 

test to check verify the device against its all electrical test cases. Once device 

is enabled into any test mode, it can not be used for any other operation. 

 

External reset should be used to exit the device from the test mode. 

 

Table 4-8 

shows the Test Mode register description.

Value after Reset:

 00h

Table 4-8.  Test Mode (TEST MODE) Register Details

Bit

Access

Description

7:5

RO

Reserved

4

RW

Enable_test_mode

This bit is used to enable test mode on device selected from first four bits of this register 
for compliance test. At a time only one test mode should be selected in first four bits.

1: Test mode enable

0: Test mode disable

3

RW

Test_packet_mode

This bit is used to select Test-packet mode for compliance test.

1: test mode is selected

0: test mode is not selected

2

RW

Test_se0_mode

This bit is used to select Test-SE0 mode for compliance test.

1: test mode is selected

0: test mode is not selected

1

RW

Test_k_mode

This bit is used to select Test-K mode for compliance test.

1: test mode is selected

0: test mode is not selected

0

RW

Test_J_mode

This bit is used to select Test-J mode for compliance test.

1: test mode is selected

0: test mode is not selected

Summary of Contents for USB20SR

Page 1: ...Level Solutions Inc USA 14100 Murphy Avenue San Martin CA 95046 408 852 0067 http www slscorp com IP Core Version 1 3 Document Version 1 3 Document Date January 2013 USB 2 0 USB20SR Device IP Core Use...

Page 2: ...the suitability of the device for a specific purpose as defined by our customers SLS reserves the right to make changes to the hardware or firmware or software or to the specifications without prior...

Page 3: ...age dialog box Bookmarks serve as an additional table of contents Thumbnail icons which provide miniature preview of each page pro vide a link to the pages Numerous links shown in Navy Blue color allo...

Page 4: ...most up to date information about SLS products go to the SLS worldwide website at http www slscorp com For additional information about SLS products consult the source shown below Information Type E m...

Page 5: ...Italic type Variable names are enclosed in angle brackets and shown in italic type Example USB20SR Installation Path 1 2 Numbered steps are used in a list of items when the sequence of items is impor...

Page 6: ...1 Features 2 Core Resources 2 Further Information 3 2 Core Architecture 4 ULPI PHY 5 ULPI Interface 5 Protocol Layer 5 EndPoint Registers 5 EP0 Controller 5 On Chip RAM 6 Micro Controller Processor In...

Page 7: ...January 2013 INT_MSK 15 INT_SRC 16 MAIN_CSR 21 FRM_NAT 23 TEST MODE 24 SETUP_PACK_1 25 SETUP_PACK_2 25 ULPI_PHY_CS 25 ULPI_REG_ACCESS 26 D_SPEED_SEL 27 D_CNCT 28 Endpoint Registers 28 EPn_CSR 28 EPn_I...

Page 8: ...ided as Altera Quartus II Mega function Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system using Nios II Avalon bus This user guide will provide you with...

Page 9: ...IN OUT Configurable for up to 15 IN OUT endpoints which can support Bulk Interrupt Isochronous functionality on each endpoint on customer request at additional cost Fully software controlled CONTROL...

Page 10: ...t USB20SR IP Core installation directory structure and its content licensing component implementation and its support refer readme html located at USB20SR Installation Path usb20sr USB20SR Installatio...

Page 11: ...errupt each transfer type retains a separate pipe for OUT and IN operation Figure 2 1 illustrates overall architecture of the USB20SR IP core Figure 2 1 USB20SR Device IP Core Architecture Each of the...

Page 12: ...for each endpoints One can configure any specific endpoint through these registers via Avalon interface Detail description of each register as well as it s bit is given inside the Table 4 1 Register D...

Page 13: ...ion of the IP Core Micro controller and device interfaces with this memory through two different memory ports with separate clock for each Size of this memory should be increased through SOPC builder...

Page 14: ...ram The USB core uses onchip memory 512 32 for IN operation as well as 512 32 for OUT operation separately IN and OUT memory starts from the same location inside the IP Core 0x20000 IN memory is write...

Page 15: ...is used When the first buffer is empty full the function controller may be notified via an interrupt The function controller can refill empty buffer0 now The core will now use buffer 1 for the next op...

Page 16: ...terrupts indicate overall events that have either global meaning for all endpoints or can not be associated with an endpoint because of an error condition 2 The endpoint interrupt source register indi...

Page 17: ...determine endpoint specific events Multiple interrupt sources may be indicated at any given time Software should be prepared to handle every interrupt source it cares about A care must be taken not t...

Page 18: ...Interrupt Mask for endpoint independent interrupt sources 4 INT_SRC 0x0c 32 ROC Interrupt source register 5 MAIN_CSR 0x10 8 RW Control Status register 6 FRM_NAT 0x14 32 RO Frame number and time 7 TES...

Page 19: ...terrupt Register 28 EP3_BUFFER0 0x78 32 RW EndPoint 3 Buffer0 Register 29 EP3_BUFFER1 0x7c 32 RW EndPoint 3 Buffer1 Register 30 EP4_CSR 0x80 32 RW EndPoint 4 CSR Register 31 EP4_IMS 0x84 32 ROC EndPoi...

Page 20: ...er 55 EP10_IMS 0xE4 32 ROC EndPoint 10 Interrupt Register 56 EP10_BUFFER0 0xE8 32 RW EndPoint 10 Buffer0 Register 57 EP10_BUFFER1 0xEc 32 RW EndPoint 10 Buffer1 Register 58 EP11_CSR 0xF0 32 RW EndPoin...

Page 21: ...0x120 32 RW EndPoint 14 CSR Register 71 EP14_IMS 0x124 32 ROC EndPoint 14 Interrupt Register 72 EP14_BUFFER0 0x128 32 RW EndPoint 14 Buffer0 Register 73 EP14_BUFFER1 0x12c 32 RW EndPoint 14 Buffer1 R...

Page 22: ...n requirement The information only inter rupts can be disabled while other interrupts should be handled properly by processor for configuration of the device according to the device speed as well as d...

Page 23: ...eneration due to device is detached 5 RW Device Attach Mask 1 Enable interrupt generation due to device is attached 0 Disable interrupt generation due to device is attached 4 RW Resume Mode Mask 1 Ena...

Page 24: ...reset 0 Device is not reset 27 ROC USB Rx Error This interrupt bit is for information purpose only Device sets this interrupt whenever it finds any undesired D and D value during data receive operatio...

Page 25: ...his bit provides status of one possible error of USB communication Device sets this bit whenever any token is received with PID checksum error from host Device takes all necessary action to handle thi...

Page 26: ...vent is given inside endpoint interrupt register information 1 Interrupt bit is set inside endpoint12 0 Interrupt bit is not set inside endpoint12 11 RO Endpoint 11 interrupt Device sets this bit when...

Page 27: ...event is given inside endpoint interrupt register information 1 Interrupt bit is set inside endpoint6 0 Interrupt bit is not set inside endpoint6 5 ROs Endpoint 5 interrupt Device sets this bit when a...

Page 28: ...ter Details of the endpoint interrupt event is given inside endpoint interrupt register information 1 Interrupt bit is set inside endpoint2 0 Interrupt bit is not set inside endpoint2 1 RO Endpoint 1...

Page 29: ...e clears this bit Remote wake up should not be performed until host enables the device for remote wake up event through Set feature Device clears this bit after performing a resume request 1 Device is...

Page 30: ...e When the device is enabled for high speed mode using D_SPEED_SEL register and it is attached into full speed mode with the host then the message will be displayed that device can be connected into h...

Page 31: ...Access Description 7 5 RO Reserved 4 RW Enable_test_mode This bit is used to enable test mode on device selected from first four bits of this register for compliance test At a time only one test mode...

Page 32: ...ter as per the application requirement Table 4 11 shows the ULPI PHY Chip Enable register description Table 4 9 Setup Packet SETUP_PACK_1 Register Details Bit Access Description 31 0 RO First four byt...

Page 33: ...this bit is 1 ULPI PHY chip select should be disabled to use its IO pins in sharing mode 1 ULPI PHY chip select enable 0 ULPI PHY chip select disable Table 4 12 ULPI PHY Chip Register Read Write ULPI...

Page 34: ...regis ter during read operation 15 8 RW Phy Reg writedata These bits of the register is used to specify write data which will be loaded inside the selected PHY register when write operation is enable...

Page 35: ...s register processor can configure the endpoint with few basic functionality support It can also use this register to get back some information during communication to take few decisions based on it D...

Page 36: ...upport as per the custom request By default endpoint can perform a single direction communication either IN or out Note Control endpoint does not use this information for buffer selection and it is re...

Page 37: ...fer over this EP 10 Set EP HALT 11 Reserved 21 18 RO EP_number 17 RW LRG_OK These bits are used to show the number Endpoint numbers are fixed from hardware itself and it can not be changed through sof...

Page 38: ...ize MaxPacketSize in bytes These bits are used by device to get information of max payload size of the endpoint Dif ferent endpoint can be configured with different maximum packet length within its ma...

Page 39: ...n control endpoint 1 Setup packet is received 0 Setup packet is not received 5 ROC PID Sequence Error This interrupt bit is for information purpose only Device sets this bit whenever it receives a dat...

Page 40: ...t when out operation is finished 2 ROC Unsupported PID error This interrupt bit is for information purpose only Device sets this bit whenever it receives unsupported PID for the endpoint It means if e...

Page 41: ...esponse of IN token received for endpoint Default value after reset is 1 for this bit For IN endpoint processor resets this bit with proper setting of buffer pointer as well as size once it completes...

Page 42: ...e register Device IP Core uses this information if used bit is cleared by processor to check how many number of received bytes can be stored inside the buffer or how many number of bytes can be transm...

Page 43: ...nable register setting from assignment editor of Quartus II software Tool to implement control and data registers of bidirectional lines inside the IO pin Nxt 1 In Next line of ULPI interface Stp 1 Ou...

Page 44: ...R Device IP core in SOPC Builder follow the steps below 1 Running usb20sr_ licensetype _v version exe will automatically place the USB20SR component into SOPC Builder GUI You can see that USB20SR comp...

Page 45: ...ter is the Nios processor Using the SOPC builder tool include the Nios processor must have the Nios development kit Then add any other peripherals required for the final design and assign the base add...

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