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Time-to-Digital-Converter Octa Channel TDC Manual | Surface Concept GmbH

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Summary of Contents for Octa Channel TDC

Page 1: ...Time to Digital Converter Octa Channel TDC Release 442 443 451 461 Manual...

Page 2: ...ncept de web www surface concept de All rights reserved No part of this manual may be reproduced without the prior permission of Surface Concept GmbH User Manual for the Octa Channel TDC Release 442 4...

Page 3: ...11 4 2 Layout of the Octa Channel TDC 13 4 2 1 TDC Stop Inputs 14 4 2 2 TDC Start Input 14 4 2 3 TDC Start Output 15 4 2 4 Device Synchronization Signal Input Output 15 4 2 5 Start Frequency Divider 1...

Page 4: ...4 Time to Digital Converter Octa Channel TDC Manual Surface Concept GmbH T h i s s i d e h a s b e e n l e f t b l a n k o n p u r p o s e...

Page 5: ...llowing symbols appear throughout the manual Note The note symbol marks text passages which contain important information hints about the operation of the detector Follow these information to ensure a...

Page 6: ...6 Time to Digital Converter Octa Channel TDC Manual Surface Concept GmbH T h i s s i d e h a s b e e n l e f t b l a n k o n p u r p o s e...

Page 7: ...a Channel TDC R442 R443 R451 R461 1x USB cable R442 1x Ethernet cable R443 R451 R461 1x power cable Table 1 Packing list for the Octa Channel TDC R442 R443 R451 R461 3 2 Cabling The general connection...

Page 8: ...the Octa Channel TDC R461 to a Surface Concept Delayline Detector Figure 1b Specific connection scheme of the Octa Channel TDC R451 to a Surface Concept Delayline Detector Time to Digital Converter Oc...

Page 9: ...nated and are laid out for 50Ohm terminated LVTTL signal levels For release versions R443 R451 R461 Use the Ethernet cable to connect the Octa Channel TDC to the PC Use BNC cables to connect your addi...

Page 10: ...ation Manual Read out of the TDC is done with a standard PC via USB R442 or Ethernet R443 R451 R461 connection For the PC the following minimum system requirements are highly recommended Processor Qua...

Page 11: ...A enables a comfortable setup and a variable data stream handling from the TDC via USB and Ethernet The main delayline detector functionality is permanently programmed A complex FIFO design makes data...

Page 12: ...zed time gate in an interval from 1ms to 1193h The synchronization pulse for the external acquisition start SYNC IN is transferred directly into the FPGA that controls the acquisition process The FPGA...

Page 13: ...461 7 BNC Sockets for Device Synchronization Signal IN and OUT R442 R443 R451 R461 8 BNC Sockets for external START Input and general START Output R442 R443 R451 R461 9 BNC Socket for STATE Input R442...

Page 14: ...ust be set to accept external start signals by changing the corresponding entry in the tdc_gpx3 ini file The corresponding entry in the tdc_gpx3 ini file is Ext_Gpx_Start X X is either NO or YES The d...

Page 15: ...ta acquisition can be synchronized to an external signal for various measurement applications linked to external devices This device synchronization signal has to be applied as LVTTL signal to the SYN...

Page 16: ...ing the external start input Herewith the frequency divider can operate with different dividing factors which can be set within the software to always guarantee a start frequency of below 9MHz The fre...

Page 17: ...and is therefore functioning as a timer Any signal to the TAG IN is ignored This mode is not working in combination with the state input the tag is counting the external LVTTL signal applied to the TA...

Page 18: ...80MHz clock signal of the FPGA A signal on TAG IN resets the timer to 0 must be set for using the state input Hereby the state input functions in combination with the tag signal functioning as a count...

Page 19: ...corresponding entry in the tdc_gpx3 ini file is Measurement_to_Start_Sync X X is either NO or YES The default setting is NO Measruement_to_Start_Sync YES must be set for the TDC to provide the gate ou...

Page 20: ...an internal service module which handles its own separate IP address which can be received from any local network via DHCP Commands to change the IP address must be passed as command lines via this s...

Page 21: ...tart frequency divider 2 4 8 16 and 32 fold divider Dynamic range 2E19 All channels provide precisely an equal resolution 32 fold multi hit capability per channel 80MHz internal device measurement rat...

Page 22: ...32 fold divider Dynamic range 2E19 All channels provide precisely an equal resolution 32 fold multi hit capability per channel 80MHz internal device measurement rate Stop Signal Input Low voltage PECL...

Page 23: ...cy divider 2 4 8 16 and 32 fold divider Dynamic range 2E19 All channels provide precisely an equal resolution 32 fold multi hit capability per channel 80MHz internal device measurement rate Stop Signa...

Page 24: ...annels provide precisely an equal resolution 32 fold multi hit capability per channel 80MHz internal device measurement rate Stop Signal Input Low voltage PECL differential signal on 1x differential m...

Page 25: ...ecific connection scheme of the Octa Channel TDC R451 to a Surface Concept Delayline Detector 8 Figure 1c Specific connection scheme of the Octa Channel TDC R461 to a Surface Concept Delayline Detecto...

Page 26: ...ean directive 89 336 EEC Electromagnetic Compability Directive amended by 91 263 EEC and 92 31 EEC and 93 68 EEC 73 23 EEC Low Voltage Equipment Directive amended by 93 68 EEC The compliance of the ab...

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