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Time-to-Digital Converter Octa Channel TDC Manual
4 TDC Layout
4.1 Schematic Description of the Octa Channel TDC
The Octa Channel TDC series combines the excellent performance of the GPX TDC chip with a high speed
USB (R442) or an Ethernet interface (R443, R451, R461).
A field programmable gate array (FPGA) enables a comfortable setup and a variable data stream handling
from the TDC via USB and Ethernet.
The main delayline detector functionality is permanently programmed. A complex FIFO design makes
data losses almost impossible. The user DLL controls the data handling and streaming for the user.
The following brief description about the internal structure of the measurement unit is only informative:
Figure 2a: TDC block diagram (R442).
Time-to-Digital-Converter Octa Channel TDC Manual | Surface Concept GmbH
