Supero X7SBU, User Manual

Page: 15 / 89

Chapter 1: Introduction
1-9
1-4 Chipset Overview
The Intel
®
X48 Express chipset, designed for use with an Intel
®
Xeon
®
3000 se-
quence/Core
TM
2 Extreme/Core
TM
2 Quad/Core
TM
2 Duo processor in the LGA 775
Land Grid Array Package, is comprised of two primary components: the Memory
Controller Hub (MCH) and the I/O Controller Hub (ICH9R). The X7SBU provides
the performance and feature-set required for the mainstream server market.
Note: The Intel
®
X48 chipset does not support add-in graphics cards in the
PCI-E interface by the Memory Controller Hub
Memory Controller Hub (X48)
The function of the MCH is to manage the data flow between four interfaces: the
CPU interface, the DDR3 System Memory interface, the PCI Express interface,
and the Direct Media Interface (DMI). The MCH is optimized for the Xeon
®
3000
sequence/Core
TM
2 Extreme/Core
TM
2 Quad/Core
TM
2 Duo processor in the LGA775
Land Grid Array package.and supports up to 8 Gb Unbuffered DDR3 Non-ECC up
to 1333 MHz in 4 DIMMs or DDR3 Non-ECC 1600 MHz up to 4GB in 2 DIMMs
memory
I/O Controller (ICH9R)
The I/O Controller (ICH9R) provides the data buffering and interface arbitration
required for the system to operate efficiently. It also provides the bandwidth needed
for the system to maintain its peak performance. The Direct Media Interface (DMI)
provides the connection between the MCH and the ICH9R. The ICH9R supports two
PCI-Express devices, six Serial ATA ports, and up to seven USB 2.0 ports/headers.
In addition, the ICH9R offers the Intel Matrix Storage Technology which provides
various RAID options for data protection and rapid data access. It also supports the
next generation of client management through the use of PROActive technology in
conjunction with Intel's next generation Gigabit Ethernet controller.