Supero PDSLA, User Manual

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B-2
PDSLA/PDSLE User's Manual
POST (hex) Description
11h Reserved
12h Use walking 1's algorithm to check out interface in CMOS circuitry. Also set real-time
clock power status, and then check for override.
13h Reserved
14h Program cipset defaults into chipset. Chipset default values are MODBINable by
OEM customers.
15h Reserved
16h Initial Early_Init_Onboard_Generator switch.
17h Reserved
18h Detect CPU information including brand, SMI type (Cyrix or Intel) and CPU level
(586 or 686).
19h Reserved
1Ah Reserved
1Bh Initial interrupts vector table, If no special specifi ed, all H/W interrupts are directed
to SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_soft_HDLR.
1Ch Reserved
1Dh Initial EARLY_PM_INIT switch.
1Eh Reserved
1Fh Load keyboard matrix (notebook platform).
20h Reserved
21h HPM initialization (notebook platform)
22h Reserved
23h 1. Check validity of RTC value, e.g. a value of 5Ah is an invalid value for RTC
minute
2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value
instead.
3. Prepare BIOS resource map for PCI and PnP use. If ESCD is valid, take into
consideration of the ESCD's legacy information.
4. Onboard clock generator initialization. Disable respective clock resource to
empty PCI and DIMM slots.
5. Early PCI initialization:
- Enumerate PCI bus number.
- Assign memory and I/O resource.
- Search for a valid VGA device and VGA BIOS and put it into C000:0.
24h Reserved
25h Reserved
26h Reserved
27h Initialize INT 09 buffer.
28h Reserved
29h 1. Program CPU internal MTRR (P6 & PII) for 0-64K memory address.
2. Initialize the APIC for Pentium clas CPU.
3. Program early chipset according to CMOS setup. Example: onboard IDE con-
troller.
4. Measure CPU speed.
5. Invoke video BIOS.