2-14
PDSLA/PDSLE User's Manual
S
U
PE
RD
S
L
A
/PD
S
LE
PCI-E x1
®
LGA 775 Processor
KB/MS
Parallel
Port
CO
M
1
VGA
USB
3/4/5/6
USB1/2
JFUSB1
Fan3
Clock
945G/P
(Lakeport)
North Bridge
PCI-E x16
LAN
CTRL
JPL1
GLAN Enable
CD in
Aux.In
AC97
COM2
BIOS
CL CMOS
J L 1
WOL
I-SATA0
FP
C
TRL
Fa
n2
JF 1
Buzzer
ID
E
24
-Pin
AT
X
PW
R
Su
p
e
rI/
O
F/P USB7/8
ICH7
J 9
DIMM#1A
DIMM#2A
DIMM#1B
DIMM#2B
Floppy
Audio
JBT1
J 3
J 2 7
J 4 0
South Bridge
J 1 3
J 4 5
J 1 1
J44
JG1
J 3 1
J 3 0
Battery
PCI#4 -33MHz
4-Pin ATX PWR
J 4 1
J 2 8
JPUSB1
JFUSB2
J7
J 1
PCI-E x1
J 8
PC I4
PCI#3 -33MHz
PC I3
PC I2
PCI#2-33MHz
PCI#1-33MHz
PC I1
J P 1
J P 2
J PU SB 2
F/P USB Wake-up
J 4 3
I-SATA1
I-SATA2
I-SATA3
D
2
4
JWD
JLED
LE 1
J WO R
RJ45
Fan1/CPU
Slot#1
Slot#2
Slot#3
Slot#5
Slot#4
Slot#6
Slot#7
FP Aud
J12
(*PDSLA
)
Chassis Intrusion
The Chassis Intrusion header is lo-
cated at JL1. See the board layout
in Chapter 1 for the location of JL1
and the table on the right for pin
defi nitions.
Fan Headers
There are three fan headers (Fan
1, Fan 2 and Fan3) on the PDSLA/
PDSLE. (See the table on the right
for pin defi nitions.) These are 4-pin
fan headers; however, the traditional
3-wire fans are also supported. (Pins
#1-#3 of the fan headers are back-
ward compatible with the traditional 3-
pin fans.) When a 3-wire fan is used,
it will be set to run at the full speed
by default. When a 4-wire fan is used,
the CPU and chassis fan speeds will
be automatically controlled by the
control circuit inside the fan based
upon the CPU temperature.
Chassis Intrusion
Fan 2
Fan 1(CPU Fan)
Fan 3
Summary of Contents for PDSLA
Page 1: ...PDSLA PDSLE USER S MANUAL Revision 1 0...
Page 20: ...1 14 PDSLA PDSLE User s Manual Notes...
Page 50: ...2 30 PDSLA PDSLE User s Manual Notes...
Page 56: ...3 6 PDSLA PDSLE User s Manual Note...
Page 72: ...PDSLA PDSLE User s Manual 4 16 Notes...