2-10
X6DAR-8G/X6DAR-iG User's Manual
Power LED
The Power LED connection is lo-
cated on pins 15 and 16 of JF1.
Refer to the table on the right for
pin definitions.
NMI Button
The non-maskable interrupt button
header is located on pins 19 and
20 of JF1. Refer to the table on
the right for pin definitions.
Pin
Number
19
20
Definition
Control
Ground
NMI Button Pin
Definitions (JF1)
Pin
Number
15
16
Definition
Vcc
Control
PWR_LED Pin Definitions
(JF1)
K B
DIMM 4B
Mouse
USB
0/1
J 1 4
C
O
M
1
DIMM 4A
DIMM 3B
DIMM 3A
DIMM 2B
DIMM 2A
DIMM 1B
DIMM 1A
GLAN1
GLAN2
VGA
S
C
S
I C
h
B
Battery
JPG1(VGA Enable)
JPL1(LAN Enable)
RAGE-
X
GLAN
C T R L
P X H
V G A
C T R L
PCI-E x16
PCI-X 133MHz
E 7 5 2 5
(Tumwater)
North Bridge
ICH5R
( S o u t h
Bridge)
Z C R
IPMI 2.0
BIOS
S I/O
7 9 0 2
S C S I
C T R L
IDE #1
IDE #2
Floppy
SCSI Ch A
W O L
COM2
S C S I
E n a b l e
U S B 2 / 3
J D 2
J P 9
CLR CMOS
Force PW-On
W O R
S P K
S W
SCSI
Ter. A
JPA1
JBT1
S
M
B
FAN5
S
A
T
A
1
SATA0
F
P
C
T
R
L
J
F
1
F A N 2
F A N 1
2 0 - P i n P W
8-Pin
C P U
4-Pin
P W
PW SMB
P W
L E D
C h a s
Intru.
J L 1
J W D
W D
CPU1
CPU2
JPA3
JPA2
SCSI Ter. B
OH
J 3 3
J 3 4
J 1 6
J7
J14
J D 1
J A 1
J 5
J 6
J 1 2
F
A
N
4
J1B1
J1D1
J 3 8
J 3 2
J4
F
4
J4
F
5
M
e
m
o
ry
S
p
e
e
d
(*N
o
te
:4
)
J11
P W
F a i l
S P K R
PCI-Ex4
JOH1
JWOR
J P F
JS
1
JS
2
JP
1
0
3RD
PW
Detect
Alarm
Reset
JP
1
1
F A N 3
Power Button
Overheat/Fan Fail LED
1
NIC1 LED
Reset Button
2
Power Fail LED
HDD LED
Power LED
Reset
Pwr
Vcc
Vcc
Vcc
Vcc
Ground
Ground
19
20
Vcc
X
Ground
NMI
X
NIC2 LED
Vcc
NMI
PWR LED
Summary of Contents for X6DAR-8G
Page 1: ... X6DAR 8G X6DAR iG USER S MANUAL Revision 1 0 SUPER ...
Page 9: ...Chapter 1 Introduction 1 3 Introduction Figure 1 1 X6DAR 8G X6DAR iG Image ...
Page 73: ...Chapter 4 BIOS 4 19 Vcore A Vcore B P3V3 P5V N12V P12V VDD P5Vsb ...
Page 84: ...A 6 X6DAR 8G X6DAR iG User s Manual Notes ...