Supermicro X6DAR-8G, User Manual

Page: 49 / 112

Chapter 2: Installation
2-29
Signal Names
+D B(12)
+D B(13)
+D B(14)
+D B(15)
+D B(P1)
+DB(0)
+DB(1)
+DB(2)
+DB(3)
+DB(4)
+DB(5)
+DB(6)
+DB(7)
+DB(P)
GR OUND
DIF FSENS
TER MPW R
TER MPW R
RESERVED
GR OUND
+ATN
GR OUND
+BSY
+ACK
+RST
+MSG
+SEL
+C/D
+REQ
+I/O
+DB(8)
+DB(9)
+D B(10)
+D B(11)
Connector
Contact
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal Names
-DB(12)
-DB(13)
-DB(14)
-DB(15)
-DB(P1)
-DB(0)
-DB(1)
-DB(2)
-DB(3)
-DB(4)
-DB(5)
-DB(6)
-DB(7)
-DB(P)
GROUND
GROUND
TERMPW R
TERMPW R
RESERVED
GROUND
-ATN
GROUND
-BSY
-ACK
-RST
-MSG
-SEL
-C/D
-REQ
-I/O
-DB(8)
-DB(9)
-DB(10)
-DB(11)
Connector
Contact
Number
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
68-pin Ultra320 SCSI C onnectors (JA1 and JA2)
Ultra320 SCSI Connectors
(*X6DAR-8G Only)
Refer to the table below for the pin
definitions of the Ultra320 SCSI
connectors located at JA1 and JA2.
K B
DIMM 4B
M
o
u
s
e
U
S
B
0
/1
J 1 4
COM
1
DIMM 4A
DIMM 3B
DIMM 3A
DIMM 2B
DIMM 2A
DIMM 1B
DIMM 1A
GLAN1
GLAN2
VGA
S
C
S
I
C
h
B
Battery
JPG1(VGA Enable)
JPL1(LAN Enable)
RAGE-
X
GLAN
C T R L
P X H
V G A
C T R L
PCI-E x16
PCI-X 133MHz
E 7 5 2 5
(Tumwater)
North Bridge
ICH5R
( S o u t h
Bridge)
Z C R
IPMI 2.0
BIOS
S I/O
7 9 0 2
S C S I
C T R L
IDE #1
IDE #2
Floppy
SCSI Ch A
W O L
C
O
M
2
S C S I
E n a b l e
U S B 2 / 3
J D 2
J P 9
CLR CMOS
Force PW-On
W O R
S P K
S W
S
C
S
I
T
e
r. A JPA1
JBT1
S
M
B
FAN5
S
A
T
A
1
S
A
T
A
0
F
P
C
T
R
L
JF
1
F A N 2
F A N 1
2 0 - P i n P W
8-Pin
C P U 4-Pin
P W
PW SMB
P W
L E D
C h a s
Intru.
J L 1
J W D
W D
CPU1
CPU2
JPA3
JPA2
SCSI Ter. B
OH
J 3 3
J 3 4
J 1 6
J
7
J
1
4
J D 1
J A 1
J 5 J 6
J 1 2
FAN4
J1B1
J1D1
J 3 8
J 3 2
J4
F
4
J
4
F
5
M
e
m
o
ry
S
p
e
e
d
(*N
o
te
:4
)
J
1
1
P W
F a i l
S P K R
PCI-Ex4
JOH1
JWOR
J P F
J
S
1
J
S
2
JP
1
0
3RD PW Detect
Alarm Reset
JP
1
1
F A N 3
V
SCSI Ch B
Battery
JPG1(VGA Enable)
JPL1(LAN Enable)
RAGE-
X
C T R L
P X H
V G A
C T R L
ICH5R
( S o u t h
Bridge)
BIOS
7 9 0 2
S C S I
C T R L
SCSI Ch A
W O L
COM2
S C S I
E n a b l e
U S B 2 / 3
J D 2
CLR CMOS
Force PW-On
W O R
S P K
S W
SCSI Ter. A
JPA1
JBT1
P W
L E D
C h a s
Intru.
J L 1
J W D
W D
JPA3
JPA2
SCSI Ter. B
OH
J7
J14
J D 1
J A 1
S P K R
JOH1
JWOR
J P F
F A N 3
SCSI Ch. A
SCSI Ch. B