18
Chapter 1: Introduction
Figure 1-7. Motherboard Layout
1.4 Motherboard Layout
Below is a layout of the X12SPT-PT motherboard with jumper, connector and LED locations
shown. See the table on the following page for descriptions. For detailed descriptions, pinout
information and jumper settings, refer to
or the
+
PRESS FIT
X12SPT-PT
REV:1.01
BIOS LICENSE
MAC CODE
IPMI CODE
DESIGNED IN USA
BAR CODE
MH5
JHS1
SXB1
I-SA
TA4
I-SA
TA5
JSD1
JSD2
SXB3
BT1
JIPMB1
MT2_2
MT1_2
MT2_1
MT1_1
JUIDB1
JBT1
LEDM1
HDD_LED1
JPTG1
JP
AUX1
JPME2
JTPM1
JPRG1
LED2
LED1
JRK1
SXB4
MH10
MH3
MH9
MH2
MH7
MH6
MH1
JNCSI1
FAN4
FAN3
PCH
BMC
LAN
CTRL
CPLD
M.2-C2
JSD2:SA
TA DOM POWER
M.2-C1
BMC_LAN
VGA
UID-LED
COM1
JPME2:
1-2:NORMAL
2-3:ME MANUFACTURING MODE
USB 0/1 (3.0)
2-3:DISABLE
Onboard 10Gb LAN1/2
JPTG1:
1-2:ENABLE
1-2:ENABLE
2-3:DISABLE
JP
AUX1:WOL
of onboard LAN1/2
LAN2 LAN1
LEDPWR
CPU SXB3 PCIe 4.0 X16
CPU SXB4 PCIe 4.0 X16
RAID KEY
-1
CMOS CLEAR
TPM/POR
T80
JTPM1:
SUPERDOM
SA
TA DOM
+POWER
SUPERDOM
SA
TA DOM
+POWER
JSD1:SA
TA DOM POWER
CPU SXB1 PCIe 4.0 X8
S-SA
TA0-5
CPU
DIMMA1
DIMMC1
DIMMD1
DIMMB1
DIMMG1
DIMMH1
DIMME1
DIMMF1
JNCSI1
SXB4
JRK1
JTPM1
JBT1
FAN4
JHS1
SXB1
JSD1
JSD2
I-SATA4
I-SATA5
BT1
SXB3
BMC_LAN
COM1
LEDPWR
JIPMB1
FAN3
UID-LED
USB0/1(3.0)
JUIDB1
VGA
JPTG1
JPAUX1
JPME2
CPU
DIMMC1
DIMMD1
DIMMA1
DIMMB1
M.2-C1
M.2-C2
DIMMG1
DIMMH1
DIMME1
DIMMF1
LED1
LED2
LAN1
LAN2
LEDM1
HDD_LED1