Chapter 1: Introduction
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Chipset Overview
Intel’s E7205 chipset is comprised of two primary components: the Memory
Controller Hub (MCH) and the I/O Controller Hub (ICH4). The E7205 provides
the performance and feature-set required for high-end single-processor
desktop and workstation systems.
Memory Controller Hub (MCH)
The MCH includes the host (CPU) interface, memory interface, ICH4 inter-
face and 8xAGP interface for the E7205 chipset. It contains advanced
power management logic and supports dual channel DDR SDRAM DIMM
slots. The AGP 3.0 interface supports 8x data transfers and operates at a
peak bandwidth of 2032 MB/s. It supports 8xAGP cards and is backward
compatible with 4xAGP cards.
The MCH has four hub interfaces: one to communicate with the ICH4 and
three for high-speed I/O communications. The MCH employs a 144-bit wide
memory bus for a DDR-266 memory interface, which provides a maximum
total bandwidth of 4.27 GB/s. The ICH4 interface is a 266 MB/sec point-to-
point connection using an 8-bit wide, 66 MHz base clock at a 4x data
transfer rate.
I/O Controller Hub (ICH4)
The ICH4 is a fourth-generation I/O Controller Hub subsystem that integrates
many of the input/output functions of the chipset, including a two-channel
ATA100 Bus Master IDE controller. The ICH4 also interfaces with the PCI
cards, the AC'97 Audio CODEC and the various communications ports.
Nearly all communications between the MCH and the ICH4 takes place over
the hub Interface, which is a 66 MHz/266 MB/s bus.
Recovery from AC Power Loss
BIOS provides a setting for you to determine how the system will respond
when AC power is lost and then restored to the system. You can choose
for the system to remain powered off (in which case you must hit the
power switch to turn it back on) or for it to automatically return to a power
on state. See the Power Lost Control setting in the BIOS chapter of this
manual to change this setting. The default setting is Always OFF.
