Studer D424, Operating And Service Instructions

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D424 MO Recorder
E6/2 D424 - Circuits
SW V 1.6 Date printed: 06.03.02
Synchronization Setting
FS INTE DRP WCL AES VAREG Sampling Rate
0 1 0 0 x 768 48 kHz internal
0 1 1 0 x 768 48 kHz drop-frame internal
1 1 0 0 x 872 44.1 kHz internal
1 1 1 0 x 872 44.1 kHz drop-frame internal
0 1 0 0 x 2048-1280 (1+A) 48 kHz internal w. Varispeed A*
1 1 0 0 x 2048-1176 (1+A) 44.1 kHz int. w. Varispeed A*
0 0 x 1 0 x 48 kHz external (WCLK)
1 0 x 1 0 x 44.1 kHz external (WCLK)
0 0 x 1 1 x 48 kHz external (AES)
1 0 x 1 1 x 44.1 kHz external (AES)
0 0 0 0 x 768 48 kHz external (Video)
0 0 1 0 x 768 48 kHz drop-frame ext. (Video)
1 0 0 0 x 872 44.1 kHz external (Video)
1 0 1 0 x 872 44.1 kHz drop-frame ext. (Video)
* A range: –0.125...+
Video Composite Sync/TC Generator
VAUT
0 PLL divider defined by VR1, VR0
1 PLL divider automatically selected
VR1 VR0 Frame Rate on Sync Input/TC Generator Frame Rate
0 0 30 Hz
0 1 30 Hz drop-frame
1 0 25 Hz
FR1 FR0 Computed Frame Rate/TC Generator Frame Rate
0 0 30 Hz
0 1 30 Hz drop-frame
1 0 25 Hz
1 1 24 Hz
Frequency Measurement for Word Clock or AES/EBU Inputs
R1 R0
0 0 out of range
0 1 48 kHz (46 kHz < fs < (48 kHz + 13%))
1 0 44.1 kHz ((44.1 kHz + 13%) < fs < 46 kHz)
1 1 not used
6.1.2 Time Code
For the handling of the SMPTE time code the TC reader (IC30) and the
TC generator (IC29), and for exact synchronization with the audio signal
the controller (IC20) are responsible.
6.1.3 Audio
The audio TDM bus is linked to the core via the bi-directional register
(IC28). With the controller (IC2) and the Dual Ported RAM (IC11) the
audio data are buffered and converted to the appropriate format for the
monitor D/A converter (IC17), for the AES/EBU receiver (IC5) and the
AES/EBU transmitters (IC4).