STMicroelectronics STM32F042C4, Manual

Page: 84 / 117

R
AIN
T
S
f
ADC
C
ADC
2
N 2 +
 
ln
 
--------------------------------------------------------------
R
ADC
–

Electrical characteristics STM32F042xx
84/117 DocID025832 Rev 2
Equation 1: R
AIN
max formula
f
TRIG
(2)
External trigger frequency
f
ADC
= 14 MHz - - 823 kHz
- - 17 1/f
ADC
V
AIN
Conversion voltage range 0 - V
DDA
V
R
AIN
(2)
External input impedance
See Equation 1 and
Table 55 for details
- - 50 k

R
ADC
(2)
Sampling switch
resistance
- - 1 k

C
ADC
(2)
Internal sample and hold
capacitor
- - 8 pF
t
CAL
(2)
Calibration time
f
ADC
= 14 MHz 5.9 μ s
83 1/f
ADC
W
LATENCY
(2)
ADC_DR register write
latency
ADC clock = HSI14
1.5 ADC
2
f
PCLK
cycles
-
1.5 ADC
3
f
PCLK
cycles
ADC clock = PCLK/2 - 4.5 -
f
PCLK
cycle
ADC clock = PCLK/4 - 8.5 -
f
PCLK
cycle
t
latr
(2)
Trigger conversion latency
f
ADC
= f
PCLK
/2 = 14 MHz 0.196 μ s
f
ADC
= f
PCLK
/2 5.5 1/f
PCLK
f
ADC
= f
PCLK
/4 = 12 MHz 0.219 μ s
f
ADC
= f
PCLK
/4 10.5 1/f
PCLK
f
ADC
= f
HSI14
= 14 MHz 0.188 - 0.259 μ s
Jitter
ADC
ADC jitter on trigger
conversion
f
ADC
= f
HSI14
- 1 - 1/f
HSI14
t
S
(2)
Sampling time
f
ADC
= 14 MHz 0.107 - 17.1 μ s
1.5 - 239.5 1/f
ADC
t
STAB
(2)
Power-up time 0 0 1 μ s
t
CONV
(2)
Total conversion time
(including sampling time)
f
ADC
= 14 MHz 1 - 18 μ s
14 to 252 (t
S
for sa12.5 for
successive approximation)
1/f
ADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 μ A on I
DDA
and 60 μ A
on I
DD
should be taken into account.
2. Guaranteed by design, not tested in production.
Table 54. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit