STMicroelectronics STM32F042C4, Manual

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Electrical characteristics STM32F042xx
92/117 DocID025832 Rev 2
Figure 30. SPI timing diagram - master mode
1. Measurement points are done at CMOS levels: 0.3 V
DD
and 0.7 V
DD
.
AI6
3#+/UTPUT
#0(!
-/3)
/54054
-)3/
).0 54
#0(!
-3 ").
- 3"/54
") 4).
,3"/54
,3").
#0/,
#0/,
" ) 4/54
.33INPUT
TC3#+
TW3#+(
TW3#+,
TR3#+
TF3#+
TH-)
(IGH
3#+/UTPUT
#0(!
#0(!
#0/,
#0/,
TSU-)
TV-/ TH-/
Table 64. I
2
S characteristics
(1)
Symbol Parameter Conditions Min Max Unit
f
CK
1/t
c(CK)
I
2
S clock frequency
Master mode (data: 16 bits, Audio
frequency = 48
kHz)
1.597 1.601
MHz
Slave mode 0 6.5
t
r(CK)
I
2
S clock rise time Capacitive load C
L
= 15 pF - 10
ns
t
f(CK)
I
2
S clock fall time - 12
t
w(CKH)
I2S clock high time
Master f
PCLK
= 16 MHz, audio
frequency = 48 kHz
306 -
t
w(CKL)
I2S clock low time 312 -
t
v(WS)
WS valid time Master mode 2 -
t
h(WS)
WS hold time Master mode 2 -
t
su(WS)
WS setup time Slave mode 7 -
t
h(WS)
WS hold time Slave mode 0 -
DuCy(SCK)
I2S slave input clock duty
cycle
Slave mode 25 75 %