STMicroelectronics STM32F042C4 Manual Download Page 86

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Electrical characteristics

STM32F042xx

86/117

DocID025832 Rev 2

Figure 26. ADC accuracy characteristics

Figure 27. Typical connection diagram using the ADC

1. Refer to

AIN

, R

ADC

and C

ADC

2. C

parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7

pF). A high C

parasitic

value will downgrade conversion accuracy. To remedy

this, f

ADC

should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure

13: Power supply

scheme

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as

close as possible to the chip.

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Summary of Contents for STM32F042C4

Page 1: ...DC up to 10 channels Conversion range 0 to 3 6 V Separate analog supply 2 4 V to 3 6 V Up to 14 capacitive sensing channels for touchkey linear and rotary touch sensors Calendar RTC with alarm and per...

Page 2: ...ct memory access controller DMA 18 3 9 Interrupts and events 18 3 9 1 Nested vectored interrupt controller NVIC 18 3 9 2 Extended interrupt event controller EXTI 18 3 10 Analog to digital converter AD...

Page 3: ...imum values 44 6 1 2 Typical values 44 6 1 3 Typical curves 44 6 1 4 Loading capacitor 44 6 1 5 Pin input voltage 44 6 1 6 Power supply scheme 45 6 1 7 Current consumption measurement 46 6 2 Absolute...

Page 4: ...82 6 3 16 12 bit ADC characteristics 83 6 3 17 Temperature sensor characteristics 87 6 3 18 VBAT monitoring characteristics 87 6 3 19 Timer characteristics 87 6 3 20 Communication interfaces 88 7 Pac...

Page 5: ...22 Operating conditions at power up power down 50 Table 23 Embedded reset and power control block characteristics 50 Table 24 Programmable voltage detector characteristics 50 Table 25 Embedded interna...

Page 6: ...e 62 I2C analog filter characteristics 89 Table 63 SPI characteristics 90 Table 64 I2 S characteristics 92 Table 65 LQFP48 7 mm x 7 mm low profile quad flat package mechanical data 95 Table 66 UFQFPN4...

Page 7: ...FTf I O input characteristics 79 Figure 24 I O AC characteristics definition 82 Figure 25 Recommended NRST pin protection 83 Figure 26 ADC accuracy characteristics 86 Figure 27 Typical connection dia...

Page 8: ...STM32F042xx 8 117 DocID025832 Rev 2 Figure 49 UFQFPN28 package top view 111 Figure 50 TSSOP20 20 pin thin shrink small outline 112 Figure 51 TSSOP20 recommended footprint 113 Figure 52 TSSOP20 packag...

Page 9: ...cs of the STM32F042x microcontrollers This document should be read in conjunction with the STM32F0xxxx reference manual RM0091 The reference manual is available from the STMicroelectronics website at...

Page 10: ...the 40 to 85 C and 40 to 105 C temperature ranges from a 2 0 to 3 6 V power supply A comprehensive set of power saving modes allows the design of low power applications The STM32F042x microcontroller...

Page 11: ...interfaces SPI I2S 1 1 1 2 1 I2 C 1 USART 2 CAN 1 USB 1 CEC 1 12 bit ADC number of channels 1 9 ext 3 int 1 10 ext 3 int GPIOs 16 24 26 28 30 38 Capacitive sensing channels 7 11 13 14 14 14 Max CPU f...

Page 12: ...UW 3 2 SRUW 3 2 SRUW 7RXFK 6HQVLQJ RQWUROOHU 3 QDORJ VZLWFKHV 7 7 83 63 6 63 6 6 0 8 QGRZ 3 5 5 6 7 2 21752 3 0 7 0 5 7 0 5 ELW 7 0 5 7 0 5 7 0 5 7 0 5 86 57 86 57 0 3RZHU RQWUROOHU 7 26 0 QG LQGRZ 68...

Page 13: ...speed with 0 wait states and featuring embedded parity checking with exception generation for fail critical applications The non volatile memory is divided into two arrays 16 to 32 Kbytes of embedded...

Page 14: ...power supply for RTC external clock 32 kHz oscillator and backup registers through power switch when VDD is not present 3 5 2 Power supply supervisors The device has integrated power on reset POR and...

Page 15: ...the HSI RC and the HSE crystal oscillators are disabled The voltage regulator can also be put either in normal or in low power mode The device can be woken up from Stop mode by any of the EXTI lines T...

Page 16: ...e interrupt is generated if enabled Similarly full interrupt management of the PLL clock entry is available when necessary for example on failure of an indirectly used external crystal resonator or os...

Page 17: ...O pins are shared with digital or analog alternate functions 0 6 26 26 B 1 26 B287 26 B 1 26 B287 0 6 5 WR 3 3 08 0 2 0DLQ FORFN RXWSXW 3 6 6 3 WR EXV FRUH PHPRU DQG 0 WR FORFN LQSXW 6 6 6 6 6 WR 57 3...

Page 18: ...terrupt lines of Cortex M0 and 4 priority levels Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core...

Page 19: ...ted internal temperature sensor is suitable for applications that detect temperature changes only To improve the accuracy of the temperature sensor measurement each device is individually factory cali...

Page 20: ...red using a proven implementation based on a surface charge transfer acquisition principle It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a...

Page 21: ...QFPN28 STM32F042Fx TSSOP20 G1 3 3 3 3 3 G2 3 3 3 3 3 G3 2 2 1 2 1 0 G4 3 3 3 1 1 G5 3 3 3 3 0 Number of capacitive sensing channels 14 14 13 14 11 7 Table 7 Timer feature comparison Timer type Timer C...

Page 22: ...7 for differences Each general purpose timer can be used to generate PWM outputs or as simple time base TIM2 TIM3 STM32F042x devices feature two synchronizable 4 channel general purpose timers TIM2 is...

Page 23: ...able through the option bytes The counter can be frozen in debug mode 3 12 4 System window watchdog WWDG The system window watchdog is based on a 7 bit downcounter that can be set as free running It c...

Page 24: ...e RTC clock sources can be A 32 768 kHz external crystal A resonator or oscillator The internal low power RC oscillator typical frequency of 40 kHz The high speed external clock divided by 32 3 14 Int...

Page 25: ...NDEC LIN Master Slave capability and auto baud rate feature and has a clock domain independent from the CPU clock allowing USART1 to wake up the MCU from Stop mode The USART interfaces can be served b...

Page 26: ...ampling frequency from 8 kHz up to 192 kHz can be set by an 8 bit programmable linear prescaler When operating in master mode it can output a clock for an external audio component at 256 times the sam...

Page 27: ...charging detection according to Battery Charging Specification Revision 1 2 The USB interface implements a full speed 12 Mbit s function interface with added support for USB 2 0 Link Power Management...

Page 28: ...age pinout top view 4 3 3 3 3 3 3 3 3 3 3 3 966 9 9 2 966 3 3 3 3 3 3 3 3 3 3 9 7 1567 966 9 3 3 3 9 966 3 3 227 3 3 3 3 3 3 3 3 06 9 3 3 26 B 1 3 26 B 1 3 26 B287 3 26 B287 2 SLQ VXSSOLHG E 9 2 06 9...

Page 29: ...ckage ball out Figure 6 LQFP32 32 pin package pinout top view 06Y 9 3 3 3 966 3 3 9 3 3 1567 9 3 3 227 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 9 2 966 2 SLQ VXSSOLHG E 9 2 06 9 4 3 3 3 3 3 3 3 3 966...

Page 30: ...kage top view 1 Pin pair PA11 12 can be remapped instead of pin pair PA9 10 using the SYSCFG_CFGR1 register 3 9 1567 3 3 3 3 3 3 3 9 2 3 3 3 3 3 3 3 227 3 3 3 3 06 9 9 3 3 3 3 3 3 3 26 B 1 3 26 B287 3...

Page 31: ...inouts and pin descriptions 40 Figure 9 TSSOP20 20 pin package top view 1 Pin pair PA11 12 can be remapped instead of pin pair PA9 10 using the SYSCFG_CFGR1 register 06 9 3 26 B 1 227 3 3 26 B287 1567...

Page 32: ...in I Input only pin I O Input output pin I O structure FT 5 V tolerant I O FTf 5 V tolerant I O FM capable TTa 3 3 V tolerant I O directly connected to ADC TC Standard 3 3 V I O RST Bidirectional rese...

Page 33: ...4 C6 PC15 OSC32_OUT PC15 I O TC 1 2 OSC32_OUT 5 B5 2 2 2 2 PF0 OSC_IN PF0 I O FTf CRS_ SYNC I2C1_SDA OSC_IN 6 C5 3 3 3 3 PF1 OSC_OUT PF1 I O FTf I2C1_SCL OSC_OUT 7 D5 4 4 4 4 NRST I O RST Device rese...

Page 34: ..._IO4 EVENTOUT ADC_IN7 18 F3 14 14 14 PB0 I O TTa TIM3_CH3 TIM1_CH2N TSC_G3_IO2 EVENTOUT ADC_IN8 19 F2 15 15 15 14 PB1 I O TTa TIM3_CH4 TIM14_CH1 TIM1_CH3N TSC_G3_IO3 ADC_IN9 20 D2 16 PB2 I O FT TSC_G3...

Page 35: ..._CH3 TIM17_BKIN TSC_G4_IO2 I2C1_SDA 32 C2 21 21 19 4 17 4 PA11 I O FTf 3 CAN_RX USART1_CTS TIM1_CH4 COMP1_OUT TSC_G4_IO3 EVENTOUT I2C1_SCL USB_DM 33 A1 22 22 20 4 18 4 PA12 I O FTf 3 CAN_TX USART1_RTS...

Page 36: ...I2C1_SMBA TIM16_BKIN TIM3_CH2 WKUP6 42 C4 29 29 27 PB6 I O FTf I2C1_SCL USART1_TX TIM16_CH1N TSC_G5_I03 43 A4 30 30 28 PB7 I O FTf I2C1_SDA USART1_RX USART4_CTS TIM17_CH1N TSC_G5_IO4 44 31 PF11 BOOT0...

Page 37: ...ction then depends on the content of the RTC registers which are not reset by the system reset For details on how to manage these GPIOs refer to the RTC domain and RTC register descriptions in the ref...

Page 38: ...M14_CH1 PA5 SPI1_SCK I2S1_CK CEC TIM2_CH1_ETR TSC_G2_IO2 PA6 SPI1_MISO I2S1_MCK TIM3_CH1 TIM1_BKIN TSC_G2_IO3 TIM16_CH1 EVENTOUT PA7 SPI1_MOSI I2S1_SD TIM3_CH2 TIM1_CH1N TSC_G2_IO4 TIM14_CH1 TIM17_CH1...

Page 39: ...TSC_G5_IO1 PB4 SPI1_MISO I2S1_MCK TIM3_CH1 EVENTOUT TSC_G5_IO2 TIM17_BKIN PB5 SPI1_MOSI I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA PB6 USART1_TX I2C1_SCL TIM16_CH1N TSC_G5_IO3 PB7 USART1_RX I2C1_SDA TIM17...

Page 40: ...Pinouts and pin descriptions STM32F042xx 40 117 DocID025832 Rev 2 Table 16 Alternate functions selected through GPIOF_AFR registers for port F Pin name AF0 AF1 PF0 CRS_SYNC I2C1_SDA PF1 I2C1_SCL...

Page 41: ...5 Memory mapping Figure 10 STM32F042x memory map 06 9 5HVHUYHG 3HULSKHUDOV 65 0 ODVK PHPRU 5HVHUYHG 6 VWHP PHPRU 2SWLRQ E WHV ODVK V VWHP PHPRU RU 65 0 GHSHQGLQJ RQ 227 FRQILJXUDWLRQ 5HVHUYHG 2 3 3 5...

Page 42: ...ASH Interface 0x4002 1400 0x4002 1FFF 3 KB Reserved 0x4002 1000 0x4002 13FF 1 KB RCC 0x4002 0400 0x4002 0FFF 3 KB Reserved 0x4002 0000 0x4002 03FF 1 KB DMA 0x4001 8000 0x4001 FFFF 32 KB Reserved APB 0...

Page 43: ...eserved 0x4000 5400 0x4000 57FF 1 KB I2C1 0x4000 4800 0x4000 53FF 3 KB Reserved 0x4000 4400 0x4000 47FF 1 KB USART2 0x4000 3C00 0x4000 43FF 2 KB Reserved 0x4000 3800 0x4000 3BFF 1 KB SPI2 0x4000 3400...

Page 44: ...efer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 6 1 2 Typical values Unless otherwise specified typical data are based on TA 25 C VDD VDDA 3 3...

Page 45: ...capacitors as shown above These capacitors must be placed as close as possible to or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device 9 2 9 06Y 9 H...

Page 46: ...Electrical characteristics STM32F042xx 46 117 DocID025832 Rev 2 6 1 7 Current consumption measurement Figure 14 Current consumption measurement scheme 06 9 9 7 9 9 B9 7 9 2...

Page 47: ...supply in the permitted range Symbol Ratings Min Max Unit VDD VSS External main supply voltage 0 3 4 0 V VDDIO2 VSS External I O supply voltage 0 3 4 0 V VDDA VSS External analog supply voltage 0 3 4...

Page 48: ...d VSS VSSA pins must always be connected to the external power supply in the permitted range 2 This current consumption must be correctly distributed over all I Os and control pins The total output cu...

Page 49: ...DA 0 3 FT and FTf I O 0 3 5 5 1 PD Power dissipation at TA 85 C for suffix 6 or TA 105 C for suffix 7 2 LQFP48 364 mW UFQFPN48 606 WLCSP36 313 LQFP32 351 UFQFPN32 526 UFQFPN28 170 TSSOP20 263 TA Ambie...

Page 50: ...ter Conditions Min Typ Max Unit VPOR PDR 1 1 The PDR detector monitors VDD and also VDDA if kept enabled in the option bytes The POR detector monitors only VDD Power on power down reset threshold Fall...

Page 51: ...g edge 2 66 2 78 2 9 V VPVDhyst 1 PVD hysteresis 100 mV IDD PVD PVD current consumption 0 15 0 26 1 A 1 Guaranteed by design not tested in production Table 24 Programmable voltage detector characteris...

Page 52: ...refetch OFF from 0 to 24 MHz 1 wait state and Prefetch ON above 24 MHz When the peripherals are enabled fPCLK fHCLK The parameters given in Table 26 to Table 30 are derived from tests performed under...

Page 53: ...ypass PLL on 48 MHz 12 3 15 0 3 16 0 16 2 3 2 9 3 2 3 3 3 3 4 3 32 MHz 8 5 10 6 11 2 11 7 1 9 2 1 2 2 2 5 24 MHz 6 5 8 1 8 5 8 7 1 6 1 8 1 8 1 9 HSEbypass PLL off 8 MHz 2 3 3 0 3 1 3 2 0 7 0 8 0 8 0 9...

Page 54: ...s PLL off 8 MHz 2 7 3 7 4 2 4 5 3 5 4 7 5 2 5 5 1 MHz 2 7 3 7 4 2 4 2 3 6 4 7 5 2 5 5 HSI clock PLL on 48 MHz 220 242 251 254 242 264 275 279 32 MHz 173 193 200 202 191 211 219 221 24 MHz 151 169 175...

Page 55: ...9 1 0 1 1 2 0 2 5 3 0 IDDA Supply current in Stop mode V DDA monitoring ON Regulator in stop mode all oscillators OFF 2 0 2 1 2 2 2 4 2 5 2 7 3 5 3 5 4 5 Regulator in low power mode all oscillators OF...

Page 56: ...requencies greater than 8 MHz AHB prescaler of 2 4 8 and 16 is used for the frequencies 4 MHz 2 MHz 1 MHz and 500 kHz respectively Table 29 Typical and maximum current consumption from the VBAT supply...

Page 57: ...disabled Peripherals enabled Peripherals disabled IDD Current consumption from VDD supply 48 MHz 20 7 12 8 12 3 3 4 mA 36 MHz 15 9 9 9 9 5 2 7 32 MHz 14 3 9 0 8 5 2 5 24 MHz 11 0 7 1 6 6 2 1 16 MHz 7...

Page 58: ...configured as analog inputs Caution Any floating input pin can also settle to an intermediate voltage level or switch inadvertently as a result of external electromagnetic noise To avoid current consu...

Page 59: ...3 V CEXT 0 pF C CINT CEXT CS 4 MHz 0 18 8 MHz 0 37 16 MHz 0 76 24 MHz 1 39 48 MHz 2 188 VDDIOx 3 3 V CEXT 10 pF C CINT CEXT CS 4 MHz 0 32 8 MHz 0 64 16 MHz 1 25 24 MHz 2 23 48 MHz 4 442 VDDIOx 3 3 V C...

Page 60: ...otherwise mentioned The given value is calculated by measuring the current consumption with all peripherals clocked off with only one peripheral clocked on Ambient operating temperature and supply vol...

Page 61: ...6 USART2 6 5 USB 6 6 WWDG 2 2 ALL APB Peripherals 153 8 1 The BusMatrix is automatically active when at least one master is ON CPU DMA 2 The APB Bridge is automatically active when at least one periph...

Page 62: ...mode During wakeup from Stop or Standby mode SYSCLK takes the default setting HSI 8 MHz The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode The wakeup source from Stan...

Page 63: ...rm is shown in Figure 15 High speed external clock source AC timing diagram Figure 15 High speed external clock source AC timing diagram Table 34 High speed external user clock characteristics Symbol...

Page 64: ...shown in Figure 16 Figure 16 Low speed external clock source AC timing diagram Table 35 Low speed external user clock characteristics Symbol Parameter 1 Conditions Min Typ Max Unit fLSE_ext User exte...

Page 65: ...n of CL1 and CL2 PCB and MCU pin capacitance must be included 10 pF can be used as a rough estimate of the combined pin and board capacitance when sizing CL1 and CL2 Note For information on selecting...

Page 66: ...042xx 66 117 DocID025832 Rev 2 Figure 17 Typical application with an 8 MHz crystal 1 REXT value depends on the crystal characteristics 06 9 0 UHVRQDWRU 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV LDV FRQWURO...

Page 67: ...T website www st com Table 37 LSE oscillator characteristics fLSE 32 768 kHz Symbol Parameter Conditions 1 Min 2 Typ Max 2 Unit IDD LSE current consumption LSEDRV 1 0 00 lower driving capability 0 5 0...

Page 68: ...2 Figure 18 Typical application with a 32 768 kHz crystal Note An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one 06 9 26 B287 26 B 1 I 6 N UHVRQDWRU 5H...

Page 69: ...curacy characterization results Table 38 HSI oscillator characteristics 1 1 VDDA 3 3 V TA 40 to 105 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit fHSI Frequency 8 MHz TRIM...

Page 70: ...er Conditions Min Typ Max Unit fHSI14 Frequency 14 MHz TRIM HSI14 user trimming step 1 2 2 Guaranteed by design not tested in production DuCy HSI14 Duty cycle 45 2 55 2 ACCHSI14 Accuracy of the HSI14...

Page 71: ...Min Typ Max Unit fHSI48 Frequency 48 MHz TRIM HSI48 user trimming step 0 09 2 0 14 0 2 2 DuCy HSI48 Duty cycle 45 2 2 Guaranteed by design not tested in production 55 2 ACCHSI48 Accuracy of the HSI48...

Page 72: ...Unit fLSI Frequency 30 40 50 kHz tsu LSI 2 2 Guaranteed by design not tested in production LSI oscillator startup time 85 s IDDA LSI 2 LSI oscillator power consumption 0 75 1 2 A Table 42 PLL characte...

Page 73: ...nd VSS through a 100 pF capacitor until a functional disturbance occurs This test is compliant with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results ar...

Page 74: ...an be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application...

Page 75: ...gurable I O pin These tests are compliant with EIA JESD 78A IC latch up standard 6 3 13 I O current injection characteristics As a general rule current injection to the I O pins due to external voltag...

Page 76: ...characteristics General input output characteristics Unless otherwise specified the parameters given in Table 50 are derived from tests performed under the conditions summarized in Table 21 General o...

Page 77: ...ce 5 pF 1 Data based on design simulation only Not tested in production 2 The leakage could be higher than the maximum value if negative current is injected on adjacent pins Refer to Table 49 I O curr...

Page 78: ...of these requirements is shown in Figure 22 for standard I Os and in Figure 23 for 5 V tolerant I Os The following curves are design simulation results not tested in production Figure 22 TC and TTa I...

Page 79: ...tics 94 Figure 23 Five volt tolerant FT and FTf I O input characteristics 0 0 5 1 1 5 2 2 5 3 1 6 1 8 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 TTL standard requirement TTL standard requirement TTL standard req...

Page 80: ...1 Output voltage characteristics 1 Symbol Parameter Conditions Min Max Unit VOL Output low level voltage for an I O pin CMOS port 2 IIO 8 mA VDDIOx 2 7 V 0 4 V VOH Output high level voltage for an I O...

Page 81: ...IO out Output rise time 125 fmax IO out Maximum frequency 3 CL 50 pF VDDIOx 2 V 1 MHz tf IO out Output fall time 125 ns tr IO out Output rise time 125 01 fmax IO out Maximum frequency 3 CL 50 pF VDDIO...

Page 82: ...idth of external signals detected by the EXTI controller 10 ns 1 The I O speed is configured using the OSPEEDRx 1 0 bits Refer to the STM32F0xxxx RM0091 reference manual for a description of GPIO Port...

Page 83: ...er up Vhys NRST NRST Schmitt trigger voltage hysteresis 200 mV RPU Weak pull up equivalent resistor 2 VIN VSS 25 40 55 k VF NRST NRST input filtered pulse 100 1 ns VNF NRST NRST input not filtered pul...

Page 84: ...ADC clock PCLK 4 8 5 fPCLK cycle tlatr 2 Trigger conversion latency fADC fPCLK 2 14 MHz 0 196 s fADC fPCLK 2 5 5 1 fPCLK fADC fPCLK 4 12 MHz 0 219 s fADC fPCLK 4 10 5 1 fPCLK fADC fHSI14 14 MHz 0 188...

Page 85: ...or 1 9 2 8 EG Gain error 2 8 3 ED Differential linearity error 0 7 1 3 EL Integral linearity error 1 2 1 7 ET Total unadjusted error fPCLK 48 MHz fADC 14 MHz RAIN 10 k VDDA 2 4 V to 3 6 V TA 25 C 3 3...

Page 86: ...igure 13 Power supply scheme The 10 nF capacitor should be ceramic good quality and it should be placed as close as possible to the chip 2 6 DPSOH RI DQ DFWXDO WUDQVIHU FXUYH 7KH LGHDO WUDQVIHU FXUYH...

Page 87: ...g time when reading the temperature 4 s 1 Guaranteed by design not tested in production 2 Measured at VDDA 3 3 V 10 mV The V30 ADC conversion result is stored in the TS_CAL1 byte Refer to Table 3 Temp...

Page 88: ...to Section 6 3 14 I O port characteristics for the I2C I Os characteristics tMAX_COUNT Maximum possible count with 32 bit counter 65536 65536 tTIMxCLK fTIMxCLK 48 MHz 89 48 s Table 60 IWDG min max ti...

Page 89: ...he analog filter characteristics Table 62 I2C analog filter characteristics 1 1 Guaranteed by design not tested in production Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are s...

Page 90: ...th NSS NSS hold time Slave mode 2Tpclk 10 tw SCKH tw SCKL SCK high and low time Master mode fPCLK 36 MHz presc 4 Tpclk 2 2 Tpclk 2 1 tsu MI tsu SI Data input setup time Master mode 4 Slave mode 5 th...

Page 91: ...m slave mode and CPHA 0 Figure 29 SPI timing diagram slave mode and CPHA 1 1 Measurement points are done at CMOS levels 0 3 VDD and 0 7 VDD DL F W DK EWhd D K KhdWhd W D K hd D E d Khd E Khd WK WK d E...

Page 92: ...Parameter Conditions Min Max Unit fCK 1 tc CK I2 S clock frequency Master mode data 16 bits Audio frequency 48 kHz 1 597 1 601 MHz Slave mode 0 6 5 tr CK I2 S clock rise time Capacitive load CL 15 pF...

Page 93: ...put valid time Slave transmitter after enable edge Slave transmitter after enable edge Master transmitter after enable edge Master transmitter after enable edge th SD_ST Data output hold time 13 tv SD...

Page 94: ...tted byte No LSB transmit receive is sent before the first byte CAN controller area network interface Refer to Section 6 3 14 I O port characteristics for more details on the input output alternate fu...

Page 95: ...pecifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Figure 33 LQFP48 7 mm x 7 mm 48 pin low profile quad flat package outline 1 Drawing is not to...

Page 96: ...6 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 ccc...

Page 97: ...arked ES are to be considered as Engineering Samples i e they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specific...

Page 98: ...e 2 All leads pads should also be soldered to the PCB to improve the lead pad solder joint life 3 There is an exposed die pad on the underside of the UFQFPN package It is recommended to connect and so...

Page 99: ...cimal digits Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 020 0 050 0 0000 0 0008 0 0020 D 6 900 7 000 7 100 0 2717 0 2756 0 2795 E 6 900 7 000 7 100 0 2717 0 2756 0 279...

Page 100: ...package top view 1 Samples marked ES are to be considered as Engineering Samples i e they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer...

Page 101: ...kage characteristics 115 Figure 39 WLCSP36 0 4 mm pitch package outline 1 Drawing is not to scale RULHQWDWLRQ UHIHUHQFH DIHU EDFN VLGH HWDLO URWDWHG 6HDWLQJ SODQH XPS E 6LGH YLHZ HWDLO H H H EDOO ORFD...

Page 102: ...555 0 525 0 585 0 0219 0 0207 0 0230 A1 0 175 0 0069 A2 0 380 0 0150 A3 2 2 Back side coating 0 025 0 0010 b 3 3 Dimension is measured at the maximum bump diameter parallel to primary datum Z 0 250 0...

Page 103: ...6 package top view 1 Samples marked E are to be considered as Engineering Samples i e they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer...

Page 104: ...C B 5 0 MM 3 4 0 0 4 4 CCC 7 7 E Table 68 LQFP32 7 mm x 7 mm 32 pin low profile quad flat package mechanical data Symbol millimeters inches 1 Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 00...

Page 105: ...8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0...

Page 106: ...kage top view 1 Samples marked ES are to be considered as Engineering Samples i e they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qua...

Page 107: ...sed in the pinout table Seating plane ddd C C A3 A1 A D e 9 16 17 24 32 Pin 1 ID R 0 30 8 E L L D2 1 b E2 A0B8_ME Bottom view Table 69 UFQFPN32 5 x 5 mm 32 lead ultra thin fine pitch quad flat no lead...

Page 108: ...ng sample marking is shown Figure 46 UFQFPN32 package top view 1 Samples marked E are to be considered as Engineering Samples i e they are intended to be sent to customer for electrical compatibility...

Page 109: ...0LANE ETAIL 6 Table 70 UFQFPN28 4 x 4 mm 28 lead ultra thin fine pitch quad flat no lead package mechanical data Symbol millimeters inches 1 Min Typ Max Min Typ Max A 0 5 0 55 0 6 0 0197 0 0217 0 0236...

Page 110: ...eristics STM32F042xx 110 117 DocID025832 Rev 2 Figure 48 UFQFPN28 recommended footprint 1 Dimensions are in millimeters 2 All leads pads should also be soldered to the PCB to improve the lead pad sold...

Page 111: ...N28 package top view 1 Samples marked E are to be considered as Engineering Samples i e they are intended to be sent to customer for electrical compatibility evaluation and may be used to start custom...

Page 112: ...0118 c 0 09 0 2 0 0035 0 0079 D 2 6 4 6 5 6 6 0 252 0 2559 0 2598 E 6 2 6 4 6 6 0 2441 0 252 0 2598 E1 3 4 3 4 4 4 5 0 1693 0 1732 0 1772 e 0 65 0 0256 L 0 45 0 6 0 75 0 0177 0 0236 0 0295 L1 1 0 0394...

Page 113: ...le marking is shown Figure 52 TSSOP20 package top view 1 Samples marked E are to be considered as Engineering Samples i e they are intended to be sent to customer for electrical compatibility evaluati...

Page 114: ...epresents the maximum power dissipation on output pins where PI O max VOL IOL VDD VOH IOH taking into account the actual VOL IOL and VOH IOH of the I Os at low and high level in the application 7 2 1...

Page 115: ...ble 73 Ordering information scheme Example STM32 F 042 C 6 T 6 x Device family STM32 ARM based 32 bit microcontroller Product type F General purpose Sub family 042 STM32F042xx Pin count F 20 pins G 28...

Page 116: ...top and Standby modes Table 29 Typical and maximum current consumption from the VBAT supply Table 30 Typical current consumption code executing from Flash running from HSE 8 MHz crystal Table 43 Flash...

Page 117: ...NT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN A SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH...

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