Step Technica MKY02, User Manual

Page: 69 / 73

Chapter 5 Ratings
5 - 7
5.2.5 Timing of Receive Monitor Pin of Individual Port (RLLD, RLDT, RLCK)
Symbol Name Min. Typ. Max. Unit
T
RLLD
Monitor status update interval
(2
17
-1)
×
T
AX1
(2
17
)
×
T
AX1
(2
17
+1)
×
T
AX1
ns
T
RLLL
RLDT output time (2 15 -1) × T
AX1
(2 15 ) × T
AX1
(2 15 +1) × T
AX1
ns
T
RLD
RLDT bit time
(2
12
-1)
×
T
AX1
(2
12
)
×
T
AX1
(2
12
+1)
×
T
AX1
ns
T
RLDS
RLDT Setup (2
11
-1) × T
AX1
(2
11
) × T
AX1
(2
11
+1) × T
AX1
ns
T
RLDH
RLDT Hold
(2
11
-1)
×
T
AX1
(2
11
)
×
T
AX1
(2
11
+1)
×
T
AX1
ns
T
RLCH
RLCK High level width
(2
11
-1) × T
AX1
(2
11
) × T
AX1
(2
11
+1) × T
AX1
ns
T
RLCL
RLCK Low level width (2 11 -1) × T
AX1
(2 11 ) × T
AX1
(2 11 +1) × T
AX1
ns