Step Technica MKY02, User Manual

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MKY02 User’s Manual
(for Hi-speed Link System)
2 - 4
Table 2-1 lists the pin functions of the MKY02.
Table 2-1 Pin Functions of MKY02
Pin name Pin No. Logic I/O Function
RXD1 to
RXD7
2 to 5
15, 18, 19
Positive I
Input pins that input response packets (RP) from satellite ICs
Connect to output pins target port receivers. When multiple ports input signals simulta-
neously, priority is given to pins with smaller port number. Fix these pins at High or Low
when not in use.
TXE1 to
TXE7
6 to 9
12 to 14
Positive O
These pins go High when the ports of satellite ICs are enabled for sending
Connect to gate pins of target port drivers.
Leave these pins open when not in use.
TXD17 11 Positive O
Output pin that output command packets (CP) to ports of satellite ICs
Connect to input pins of port 1 to 7 drivers.
COE1 20 Positive O
Output pin for cascade connection
Connect to the CIE1 pin of the MKY02 for lower cascade connection.
Leave this pin open when it is not cascade-connected.
COP1 21 Positive O
Output pin for cascade connection
Connect to the CIP1 pin of the MKY02 for lower cascade connection.
Leave this pin open when is not cascade-connected.
COD1 22 Positive O
Output pin for cascade connection
Connect to the CID1 pin of the MKY02 for lower cascade connection.
Leave this pin open when is not cascade-connected.
COHR 23 Positive O
Output pin for cascade connection
Connect to the CIHR pin of the MKY02 for lower cascade connection.
Leave this pin open when is not cascade-connected.
CIE2 25 Positive I
Input pin for cascade connection
Connect to the COE2 pin of the MKY02 for lower cascade connection.
Fix this pin at Low when is not cascade-connected.
CIP2 26 Positive I
Input pin for cascade connection
Connect to the COP2 pin of the MKY02 for lower cascade connection.
Fix this pin at Low when it is not cascade-connected.
CID2 27 Positive I
Input pin for cascade connection
Connect to the COD2 pin of the MKY02 for lower cascade connection.
Fix this pin at Low when is not cascade-connected.
N.C. 28 Positive O
Be sure to leave this pin open.
RLDT 29 Positive O
Data signal output pin for receive monitor LED drive circuit of individual port
Leave this pin open when it is not used.
RLCK 30 Positive O
Data clock output pin for receiving monitor LED drive circuit of individual port
Leave this pin open when it is not used.
RLLD 31 Positive O
Data load signal output pin for receiving monitor LED drive circuit of individual port
Leave this pin open when it is not used.
Xi 34 Positive I
External clock input pin (48 MHz recommended)
#RST 35 Negative I
MKY02 hardware reset input pin
Keep this pin Low for 10 or more clocks of the clock to be input to the AX0 pin immedi-
ately after power-on or when resetting hardware intentionally.
AXS0 36 Positive O
Cascade clock output pin
For details, refer to
“3.2.2 Setting Cascade Clock and Baud Rate”
.
AX0 37 Positive I
Cascade clock input pin
For details, refer to
“3.2.2 Setting Cascade Clock and Baud Rate”
.
AX1 39 Positive I
Cascade clock input pin
For details, refer to
“3.2.2 Setting Cascade Clock and Baud Rate”
.
AXS1 40 Positive O
Cascade clock output pin
For details, refer to
“3.2.2 Setting Cascade Clock and Baud Rate”
.
AXS2 42 Positive O
Cascade clock output pin
For details, refer to
“3.2.2 Setting Cascade Clock and Baud Rate”
.
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