ST STM32F10 Series, Application Note

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Power supplies AN2586 - Application note
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Figure 2.
Power supply scheme
1. Optional. If a separate, external reference voltage is connected on V
REF+
, the two capacitors (10 nF and
1 µF) must be connected.
2. V
REF
+ is either connected to V
DDA
or to V
REF
.
1.3 Reset & power supply supervisor
1.3.1 Power on reset (POR) / power down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting from
2 V.
The device remains in the Reset mode as long as V
DD
is below a specified threshold,
V
POR/PDR
, without the need for an external reset circuit. For more details concerning the
power on/power down reset threshold, refer to the electrical characteristics in the
STM32F101xx and STM32F103xx datasheets.
Figure 3. Power on reset/power down reset waveform
V
BAT
STM32F10xxx
5 × 100 nF
V
DD
+ 1 × 10 µF
10 nF + 1 µF
10 nF + 1 µF
(note 1)
Battery
V
BAT
V
REF+
V
DDA
V
SSA
V
REF–
V
DD 1/2/3/4/5
V
SS 1/2/3/4/5
V
REF
V
DD
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V
DD
POR
PDR
40 mV
hysteresis
Temporization
t
RSTTEMPO
RESET
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