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AN2586 - Application note

Reference design

 21/23

Figure 14.

STM32F10xxx microcontroller reference schematic

BT1

CR1220 holder

1

4

3

2

B1

RESET

C13

100 nF

C6

20 pF

C5

20 pF

X2

8 MHz

4

3

2

X1

MC306-G-06Q-32.768 (manufacturer JFVNY)

C1

10 pF

C2

10 pF

C3

1 µF

C4

10 nF

JP1

VCC

C11

100 nF

C10

100 nF

C9

100 nF

C12

100 nF

VDD

C8

100 nF

PB5

PB6

PB7

PA4

PA5

PA6

PA7

R6

10 k

VCC

2

3

1

SW2

PA11

PA12

PE0

PD0

PD1

PA9

PA10

PD3

PD4

PD5

PD6

PC10

PC11

PB12

PB13

PB14

PB15

PB10

PB11

PC12

PE14

RESET#

PB8

PC5

PA0

PB9

PC13

PD8

PD9

PD10

PD11

PD12

PC6

PC7

PC8

PC9

0

PE15

PE9

PE8

PE11

PE10

PE12

PE13

PA1

PC1

PC2

PC3

PD13

PD2

PE1

PB1

PB2

PA15

PB3

PD14

PB0

PC4

PE2

PE3

PE4

PE5

PE6

PA3

PA13

PA14

PB4

PC0

PA2

PA8

PD7

PD15

PE7

PC14

PC15

OSC_IN

OSC_OUT

BOOT0

VDD

TP1

MCO

VDD

VBAT

OSC_IN

12

OSC_OUT

13

NRST

14

PA0-WKUP/USART2_CTS/ADC_IN0/TIM2_CH1_ETR

23

PA1/USART2_RTS/ADC_IN1

24

PA2/USART2_TX/ADC_IN2/

25

PA3/USART2_RX/ADC_IN3/

26

PA4/SPI1_NSS/USART2_CK/ADC_IN4

29

PA5/SPI1_SCK/ADC_IN5

30

PA6/SPI1_MISO/ADC_IN6/TIM3_CH1

31

PA7/SPI1_MOSI/ADC_IN7/TIM3_CH2

32

PB0/ADC_IN8/TIM3_CH3

35

PB1/ADC_IN9/TIM3_CH4

36

PB2 / BOOT1

37

PB10/I2C2_SCL/USART3_TX

47

PB11/I2C2_SDA /

48

PB12/SPI2_NSS /I2C2_SMBAl/USART3_CK /TIM1_BKIN

51

PB13/SPI2_SCK /USART3_CTS /TIM1_CH1N

52

PB14/SPI2_MISO /USART3_RTS /TIM1_CH2N

53

PB15/SPI2_MOSI/TIM1_CH3N

54

PA8/USART1_CK/

TIM1_CH1/MCO

67

PA9/USART1_TX/TIM1_CH2

68

PA10/USART1_RX/TIM1_CH3

69

PA11 / USART1_CTS/CANRX / USBDM (2)/TIM1_CH4

70

PA12 / USART1_RTS/CANTX / USBDP (2)/TIM1_ETR

71

PA13/JTMS-SWDAT

72

Not connected

73

PA14/JTCK-SWCLK

76

PA15/JTDI

77

PB3/JTDO

89

PB4/JTRST

90

PB5/I2C1_SMBAl

91

PB6/I2C1_SCL/TIM4_CH1

92

PB7/I2C1_SDA/

93

BOOT0

94

PB8/TIM4_CH3

95

PB9/TIM4_CH4

96

PE2

1

PE3

2

PE4

3

PE5

4

PE6

5

PC13-ANTI_TAMP

7

PC14-OSC32_IN

8

PC15-OSC32_OUT

9

PC0/ADC_IN10

15

PC1/ADC_IN11

16

PC2/ADC_IN12

17

PC3/ADC_IN13

18

PC4/ADC_IN14

33

PC5/ADC_IN15

34

PE7

38

PE8

39

PE9

40

PE10

41

PE11

42

PE12

43

PE13

44

PE14

45

PE15

46

PD8

55

PD9

56

PD10

57

PD11

58

PD12

59

PD13

60

PD14

61

PD15

62

PC6

63

PC7

64

PC8

65

PC9

66

PC10

78

PC11

79

PC12

80

PD0

81

PD1

82

PD2/TIM3_ETR

83

PD3

84

PD4

85

PD5

86

PD6

87

PD7

88

PE0/TIM4_ETR

97

PE1

98

U1A

STM32F103VBH6

VSS_5

10

VSSA

19

VREF-

20

VREF+

21

VDDA

22

VSS_4

27

VSS_1

49

VSS_2

74

VSS_3

99

VBAT

6

VDD_5

11

VDD_4

28

VDD_1

50

VDD_2

75

VDD_3

100

U1B

STM32F103VBH6

R5

10 k

VCC

2

3

1

SW1

BOOT1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

CN1

JTAG

TMS/SWDIO

TDI

TDO

TCK/SWCLK

RESET#

VCC

TRST

R3

10 k

R4

10 k

R2

10 k

RTCK

DBGRQ

DBGACK

JTAG connector

C7

4.7 µF

Notes:

- Capacitors (C3,C4,C7-12) should be placed on the PCB tracks closest to the VDD, VDDA and GND pins of the Microcontrollers

- VCC: mains power supply: the range is between 2.0  and 3.6 Volts (see Section 1 Power supplies)

- The value of R

EXT

 depends on the crystal characteristics. Typical value is in the range of 5 to 6 R

S

 (resonator series resistance) as indicated in Section 2.1.

ai14360

R

EXT

Summary of Contents for STM32F10 Series

Page 1: ...pment board features such as the power supply the clock management the reset control the boot mode settings and the debug management It shows how to use the STM32F10xxx product family and describes th...

Page 2: ...xternal source HSE bypass 12 2 1 2 External crystal ceramic resonator HSE crystal 12 2 2 LSE OSC clock 13 2 2 1 External source LSE bypass 13 2 2 2 External crystal ceramic resonator LSE crystal 13 2...

Page 3: ...Contents 3 23 4 3 4 SWJ debug port connection with Standard JTAG connector 19 5 Reference design 20 5 1 Main 20 5 1 1 Clock 20 5 1 2 Reset 20 5 1 3 Boot mode 20 5 2 SWJ interface 20 5 3 Power supply 2...

Page 4: ...List of tables AN2586 Application note 4 23 List of tables Table 1 Boot modes 15 Table 2 Debug port pin assignment 18 Table 3 SWJ I O pin availability 18 Table 4 Document revision history 22...

Page 5: ...esholds 9 Figure 5 Reset circuit 10 Figure 6 Clock overview 11 Figure 7 External clock 12 Figure 8 Crystal ceramic resonators 12 Figure 9 External clock 13 Figure 10 Crystal ceramic resonators 13 Figu...

Page 6: ...and shielded from noise on the PCB the ADC voltage supply input is available on a separate VDDA pin an isolated supply ground connection is provided on the VSSA pin When available depending on packag...

Page 7: ...p mode the regulator supplies low power to the 1 8 V domain preserving the contents of the registers and SRAM in Standby mode the regulator is powered off The contents of the registers and SRAM are lo...

Page 8: ...oper operation starting from 2 V The device remains in the Reset mode as long as VDD is below a specified threshold VPOR PDR without the need for an external reset circuit For more details concerning...

Page 9: ...n VDD rises above the PVD threshold depending on the EXTI Line16 rising falling edge configuration As an example the service routine can perform emergency shutdown tasks Figure 4 PVD thresholds 1 3 3...

Page 10: ...Application note 10 23 Figure 5 Reset circuit RON VDD Filter 0 1 F External reset circuit NRST System nreset WWDG reset IWDG reset POR PDR reset Software reset Low power management reset Pulse genera...

Page 11: ...peed internal clock signal LSE low speed external clock signal HSE OSC 4 16 MHz OSC_IN OSC_OUT OSC32_IN OS32_OUT LSE OSC 32 768 kHz LSI RC 32 kHz PLL x2 x3 x4 PLLMUL MCO Clock Output Main PLLXTPRE x16...

Page 12: ...configuration is shown in Figure 8 The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilizat...

Page 13: ...low power but highly accurate clock source to the real time clock peripheral RTC for clock calendar or other timing functions The resonator and the load capacitors have to be connected as close as pos...

Page 14: ...ock security system interrupt CSSI allowing the MCU to perform rescue operations The CSSI is linked to the Cortex M3 NMI non maskable interrupt exception vector If the HSE oscillator is used directly...

Page 15: ...dby mode Even when aliased in the boot memory space the related memory Flash memory or SRAM is still accessible at its original memory space After this startup delay has elapsed the CPU starts code ex...

Page 16: ...de is used to reprogram the Flash memory using one of the serial interfaces typically a UART This program is located in the system memory and is programmed by ST during production For details refer to...

Page 17: ...pin interface and a SW DP 2 pin interface The JTAG debug port JTAG DP provides a 5 pin standard JTAG interface to the AHP AP port The serial wire debug port SW DP provides a 2 pin clock data interface...

Page 18: ...w st com 4 3 3 Internal pull up and pull down on JTAG pins The JTAG input pins must not be floating since they are directly connected to flip flops to control the debug mode features Special care must...

Page 19: ...ware can then use these I Os as standard GPIOs Note The JTAG IEEE standard recommends to add pull up resistors on TDI TMS and nTRST but there is no special recommendation for TCK However for the STM32...

Page 20: ...eset The reset signal in Figure 14 is active low The reset sources include Reset button B1 Debugging tools via the connector CN1 Refer to Section 1 3 Reset power supply supervisor on page 8 5 1 3 Boot...

Page 21: ...1_TX TIM1_CH2 68 PA10 USART1_RX TIM1_CH3 69 PA11 USART1_CTS CANRX USBDM 2 TIM1_CH4 70 PA12 USART1_RTS CANTX USBDP 2 TIM1_ETR 71 PA13 JTMS SWDAT 72 Not connected 73 PA14 JTCK SWCLK 76 PA15 JTDI 77 PB3...

Page 22: ...Revision history AN2586 Application note 22 23 6 Revision history Table 4 Document revision history Date Revision Changes 12 Jul 2007 1 Initial release...

Page 23: ...IED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT...

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