ST STM32F10 Series, Application Note

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Reference design AN2586 - Application note
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5 Reference design
5.1 Main
The reference design shown in Figure 14 , is based on the STM32F10xxx, a highly
integrated microcontroller running at 72 MHz, that combines the new Cortex
™
-M3 32-bit
RISC CPU core with 128 Kbytes of embedded Flash memory and up to 20 Kbytes of high
speed SRAM
.
5.1.1 Clock
Two clock sources are used for the microcontroller:
●
X1– 32.768 kHz crystal for the embedded RTC
●
X2– 8 MHz crystal for the STM32F10xxx microcontroller
Refer to Section 2: Clocks on page 11 .
5.1.2 Reset
The reset signal in Figure 14 is active low. The reset sources include:
●
Reset button (B1)
●
Debugging tools via the connector CN1
Refer to Section 1.3: Reset & power supply supervisor on page 8 .
5.1.3 Boot mode
The STM32F10xxx is able to boot from the:
●
embedded user Flash memory
●
embedded SRAM for debugging
●
system memory
The boot option is configured by setting switches SW2 (Boot 0) and SW1 (Boot 1). Refer to
Section 3: Boot configuration on page 15 .
5.2 SWJ interface
The STM32F10xxx core integrates the serial wire / JTAG debug port (SWJ-DP). The
reference design shows the connection between the STM32F10xxx and a standard JTAG
connector. Refer to
Section 4: Debug management on page 17 .
5.3 Power supply
Refer to Section 1: Power supplies on page 6 .