AN2586 - Application note
Clocks
2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
●
HSI oscillator clock (high speed internal clock signal)
●
HSE oscillator clock (high speed external clock signal)
●
PLL clock
The devices have two secondary clock sources:
●
32 kHz low speed internal RC (LSI RC) that drives the independent watchdog and,
optionally, the RTC used for Auto Wake-up from the Stop/Standby modes.
●
32.768 kHz low speed external crystal (LSE crystal) that optionally drives the real-time
clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
the power consumption.
Figure 6.
Clock overview
1.
HSE = High-speed external clock signal; HSI = high-speed internal clock signal; LSI = low-speed internal
clock signal; LSE = low-speed external clock signal.
HSE OSC
4-16 MHz
OSC_IN
OSC_OUT
OSC32_IN
OS32_OUT
LSE OSC
32.768 kHz
LSI RC
32 kHz
PLL
x2, x3, x4
PLLMUL
MCO
Clock Output
Main
PLLXTPRE
..., x16
PLLCLK
HSI
HSE
APB1
Prescaler
/1, 2, 4, 8, 16
ADCCLK
PCLK1
HCLK
PLLCLK
to AHB bus, core,
memory and DMA
TIM2, 3, 4
x1, 2 Multiplier
USBCLK
to USB interface
to TIM2, 3
and 4
USB
Prescaler
/1, 1.5
to ADC
LSE
LSI
HSI
/2
HSI
HSE
peripherals
to APB1
Peripheral Clock
Enable (3 bits)
APB2
Prescaler
/1, 2, 4, 8, 16
PCLK2
TIM1 Timer
x1, 2 Multiplier
to TIM1
peripherals
to APB2
48 MHz
72 MHz
36 MHz max
to RTC
PLLSRC
SW
MCO
CSS
to Cortex System timer
SYSCLK
max
RTCCLK
RTCSEL[1:0]
TIM1CLK
TIMXCLK
IWDGCLK
SYSCLK
FCLK Cortex
free running clock
8 MHz
HSI RC
72 MHz max
72 MHz max
Peripheral Clock
Enable (11 bits)
Peripheral Clock
Enable (1 bit)
to independent watchdog (IWDG)
Clock
Enable (3 bits)
Peripheral Clock
Enable (13 bits)
/2
/128
/2
AHB
Prescaler
/1,2...512
/8
ADC
Prescaler
/2, 4, 6, 8
ai14367
